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13#include <asm/io.h>
14#include <asm/arch/clock.h>
15#include <asm/arch/gpio.h>
16#include <common.h>
17#include <clk.h>
18#include <dm.h>
19#include <fdt_support.h>
20#include <linux/err.h>
21#include <malloc.h>
22#include <miiphy.h>
23#include <net.h>
24#include <reset.h>
25#include <dt-bindings/pinctrl/sun4i-a10.h>
26#ifdef CONFIG_DM_GPIO
27#include <asm-generic/gpio.h>
28#endif
29
30#define MDIO_CMD_MII_BUSY BIT(0)
31#define MDIO_CMD_MII_WRITE BIT(1)
32
33#define MDIO_CMD_MII_PHY_REG_ADDR_MASK 0x000001f0
34#define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4
35#define MDIO_CMD_MII_PHY_ADDR_MASK 0x0001f000
36#define MDIO_CMD_MII_PHY_ADDR_SHIFT 12
37
38#define CONFIG_TX_DESCR_NUM 32
39#define CONFIG_RX_DESCR_NUM 32
40#define CONFIG_ETH_BUFSIZE 2048
41
42
43
44
45
46
47#define CONFIG_ETH_RXSIZE 2044
48
49#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
50#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
51
52#define H3_EPHY_DEFAULT_VALUE 0x58000
53#define H3_EPHY_DEFAULT_MASK GENMASK(31, 15)
54#define H3_EPHY_ADDR_SHIFT 20
55#define REG_PHY_ADDR_MASK GENMASK(4, 0)
56#define H3_EPHY_LED_POL BIT(17)
57#define H3_EPHY_SHUTDOWN BIT(16)
58#define H3_EPHY_SELECT BIT(15)
59
60#define SC_RMII_EN BIT(13)
61#define SC_EPIT BIT(2)
62#define SC_ETCS_MASK GENMASK(1, 0)
63#define SC_ETCS_EXT_GMII 0x1
64#define SC_ETCS_INT_GMII 0x2
65#define SC_ETXDC_MASK GENMASK(12, 10)
66#define SC_ETXDC_OFFSET 10
67#define SC_ERXDC_MASK GENMASK(9, 5)
68#define SC_ERXDC_OFFSET 5
69
70#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
71
72#define AHB_GATE_OFFSET_EPHY 0
73
74
75#define SUN8I_IOMUX_H3 2
76#define SUN8I_IOMUX_R40 5
77#define SUN8I_IOMUX 4
78
79
80#define EMAC_CTL0 0x00
81#define EMAC_CTL1 0x04
82#define EMAC_INT_STA 0x08
83#define EMAC_INT_EN 0x0c
84#define EMAC_TX_CTL0 0x10
85#define EMAC_TX_CTL1 0x14
86#define EMAC_TX_FLOW_CTL 0x1c
87#define EMAC_TX_DMA_DESC 0x20
88#define EMAC_RX_CTL0 0x24
89#define EMAC_RX_CTL1 0x28
90#define EMAC_RX_DMA_DESC 0x34
91#define EMAC_MII_CMD 0x48
92#define EMAC_MII_DATA 0x4c
93#define EMAC_ADDR0_HIGH 0x50
94#define EMAC_ADDR0_LOW 0x54
95#define EMAC_TX_DMA_STA 0xb0
96#define EMAC_TX_CUR_DESC 0xb4
97#define EMAC_TX_CUR_BUF 0xb8
98#define EMAC_RX_DMA_STA 0xc0
99#define EMAC_RX_CUR_DESC 0xc4
100
101DECLARE_GLOBAL_DATA_PTR;
102
103enum emac_variant {
104 A83T_EMAC = 1,
105 H3_EMAC,
106 A64_EMAC,
107 R40_GMAC,
108};
109
110struct emac_dma_desc {
111 u32 status;
112 u32 st;
113 u32 buf_addr;
114 u32 next;
115} __aligned(ARCH_DMA_MINALIGN);
116
117struct emac_eth_dev {
118 struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM];
119 struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM];
120 char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
121 char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
122
123 u32 interface;
124 u32 phyaddr;
125 u32 link;
126 u32 speed;
127 u32 duplex;
128 u32 phy_configured;
129 u32 tx_currdescnum;
130 u32 rx_currdescnum;
131 u32 addr;
132 u32 tx_slot;
133 bool use_internal_phy;
134
135 enum emac_variant variant;
136 void *mac_reg;
137 phys_addr_t sysctl_reg;
138 struct phy_device *phydev;
139 struct mii_dev *bus;
140 struct clk tx_clk;
141 struct clk ephy_clk;
142 struct reset_ctl tx_rst;
143 struct reset_ctl ephy_rst;
144#ifdef CONFIG_DM_GPIO
145 struct gpio_desc reset_gpio;
146#endif
147};
148
149
150struct sun8i_eth_pdata {
151 struct eth_pdata eth_pdata;
152 u32 reset_delays[3];
153 int tx_delay_ps;
154 int rx_delay_ps;
155};
156
157
158static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
159{
160 struct udevice *dev = bus->priv;
161 struct emac_eth_dev *priv = dev_get_priv(dev);
162 ulong start;
163 u32 miiaddr = 0;
164 int timeout = CONFIG_MDIO_TIMEOUT;
165
166 miiaddr &= ~MDIO_CMD_MII_WRITE;
167 miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
168 miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
169 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
170
171 miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
172
173 miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
174 MDIO_CMD_MII_PHY_ADDR_MASK;
175
176 miiaddr |= MDIO_CMD_MII_BUSY;
177
178 writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
179
180 start = get_timer(0);
181 while (get_timer(start) < timeout) {
182 if (!(readl(priv->mac_reg + EMAC_MII_CMD) & MDIO_CMD_MII_BUSY))
183 return readl(priv->mac_reg + EMAC_MII_DATA);
184 udelay(10);
185 };
186
187 return -1;
188}
189
190static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
191 u16 val)
192{
193 struct udevice *dev = bus->priv;
194 struct emac_eth_dev *priv = dev_get_priv(dev);
195 ulong start;
196 u32 miiaddr = 0;
197 int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
198
199 miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
200 miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
201 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
202
203 miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
204 miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
205 MDIO_CMD_MII_PHY_ADDR_MASK;
206
207 miiaddr |= MDIO_CMD_MII_WRITE;
208 miiaddr |= MDIO_CMD_MII_BUSY;
209
210 writel(val, priv->mac_reg + EMAC_MII_DATA);
211 writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
212
213 start = get_timer(0);
214 while (get_timer(start) < timeout) {
215 if (!(readl(priv->mac_reg + EMAC_MII_CMD) &
216 MDIO_CMD_MII_BUSY)) {
217 ret = 0;
218 break;
219 }
220 udelay(10);
221 };
222
223 return ret;
224}
225
226static int _sun8i_write_hwaddr(struct emac_eth_dev *priv, u8 *mac_id)
227{
228 u32 macid_lo, macid_hi;
229
230 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
231 (mac_id[3] << 24);
232 macid_hi = mac_id[4] + (mac_id[5] << 8);
233
234 writel(macid_hi, priv->mac_reg + EMAC_ADDR0_HIGH);
235 writel(macid_lo, priv->mac_reg + EMAC_ADDR0_LOW);
236
237 return 0;
238}
239
240static void sun8i_adjust_link(struct emac_eth_dev *priv,
241 struct phy_device *phydev)
242{
243 u32 v;
244
245 v = readl(priv->mac_reg + EMAC_CTL0);
246
247 if (phydev->duplex)
248 v |= BIT(0);
249 else
250 v &= ~BIT(0);
251
252 v &= ~0x0C;
253
254 switch (phydev->speed) {
255 case 1000:
256 break;
257 case 100:
258 v |= BIT(2);
259 v |= BIT(3);
260 break;
261 case 10:
262 v |= BIT(3);
263 break;
264 }
265 writel(v, priv->mac_reg + EMAC_CTL0);
266}
267
268static int sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 *reg)
269{
270 if (priv->use_internal_phy) {
271
272
273
274 *reg &= ~H3_EPHY_DEFAULT_MASK;
275 *reg |= H3_EPHY_DEFAULT_VALUE;
276 *reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
277 *reg &= ~H3_EPHY_SHUTDOWN;
278 *reg |= H3_EPHY_SELECT;
279 } else
280
281
282
283 *reg &= ~H3_EPHY_SELECT;
284
285 return 0;
286}
287
288static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
289 struct emac_eth_dev *priv)
290{
291 int ret;
292 u32 reg;
293
294 if (priv->variant == R40_GMAC) {
295
296 reg = readl(priv->sysctl_reg + 0x164);
297 reg |= CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
298 CCM_GMAC_CTRL_GPIT_RGMII |
299 CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY);
300
301 writel(reg, priv->sysctl_reg + 0x164);
302 return 0;
303 }
304
305 reg = readl(priv->sysctl_reg + 0x30);
306
307 if (priv->variant == H3_EMAC) {
308 ret = sun8i_emac_set_syscon_ephy(priv, ®);
309 if (ret)
310 return ret;
311 }
312
313 reg &= ~(SC_ETCS_MASK | SC_EPIT);
314 if (priv->variant == H3_EMAC || priv->variant == A64_EMAC)
315 reg &= ~SC_RMII_EN;
316
317 switch (priv->interface) {
318 case PHY_INTERFACE_MODE_MII:
319
320 break;
321 case PHY_INTERFACE_MODE_RGMII:
322 reg |= SC_EPIT | SC_ETCS_INT_GMII;
323 break;
324 case PHY_INTERFACE_MODE_RMII:
325 if (priv->variant == H3_EMAC ||
326 priv->variant == A64_EMAC) {
327 reg |= SC_RMII_EN | SC_ETCS_EXT_GMII;
328 break;
329 }
330
331 default:
332 debug("%s: Invalid PHY interface\n", __func__);
333 return -EINVAL;
334 }
335
336 if (pdata->tx_delay_ps)
337 reg |= ((pdata->tx_delay_ps / 100) << SC_ETXDC_OFFSET)
338 & SC_ETXDC_MASK;
339
340 if (pdata->rx_delay_ps)
341 reg |= ((pdata->rx_delay_ps / 100) << SC_ERXDC_OFFSET)
342 & SC_ERXDC_MASK;
343
344 writel(reg, priv->sysctl_reg + 0x30);
345
346 return 0;
347}
348
349static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev)
350{
351 struct phy_device *phydev;
352
353 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
354 if (!phydev)
355 return -ENODEV;
356
357 phy_connect_dev(phydev, dev);
358
359 priv->phydev = phydev;
360 phy_config(priv->phydev);
361
362 return 0;
363}
364
365static void rx_descs_init(struct emac_eth_dev *priv)
366{
367 struct emac_dma_desc *desc_table_p = &priv->rx_chain[0];
368 char *rxbuffs = &priv->rxbuffer[0];
369 struct emac_dma_desc *desc_p;
370 u32 idx;
371
372
373 flush_dcache_range((uintptr_t)rxbuffs, (ulong)rxbuffs +
374 RX_TOTAL_BUFSIZE);
375
376 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
377 desc_p = &desc_table_p[idx];
378 desc_p->buf_addr = (uintptr_t)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]
379 ;
380 desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
381 desc_p->st |= CONFIG_ETH_RXSIZE;
382 desc_p->status = BIT(31);
383 }
384
385
386 desc_p->next = (uintptr_t)&desc_table_p[0];
387
388 flush_dcache_range((uintptr_t)priv->rx_chain,
389 (uintptr_t)priv->rx_chain +
390 sizeof(priv->rx_chain));
391
392 writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC));
393 priv->rx_currdescnum = 0;
394}
395
396static void tx_descs_init(struct emac_eth_dev *priv)
397{
398 struct emac_dma_desc *desc_table_p = &priv->tx_chain[0];
399 char *txbuffs = &priv->txbuffer[0];
400 struct emac_dma_desc *desc_p;
401 u32 idx;
402
403 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
404 desc_p = &desc_table_p[idx];
405 desc_p->buf_addr = (uintptr_t)&txbuffs[idx * CONFIG_ETH_BUFSIZE]
406 ;
407 desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
408 desc_p->status = (1 << 31);
409 desc_p->st = 0;
410 }
411
412
413 desc_p->next = (uintptr_t)&desc_table_p[0];
414
415
416 flush_dcache_range((uintptr_t)priv->tx_chain,
417 (uintptr_t)priv->tx_chain +
418 sizeof(priv->tx_chain));
419
420 writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC);
421 priv->tx_currdescnum = 0;
422}
423
424static int _sun8i_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
425{
426 u32 reg, v;
427 int timeout = 100;
428
429 reg = readl((priv->mac_reg + EMAC_CTL1));
430
431 if (!(reg & 0x1)) {
432
433 setbits_le32((priv->mac_reg + EMAC_CTL1), 0x1);
434 do {
435 reg = readl(priv->mac_reg + EMAC_CTL1);
436 } while ((reg & 0x01) != 0 && (--timeout));
437 if (!timeout) {
438 printf("%s: Timeout\n", __func__);
439 return -1;
440 }
441 }
442
443
444 _sun8i_write_hwaddr(priv, enetaddr);
445
446 v = readl(priv->mac_reg + EMAC_TX_CTL1);
447
448 v |= BIT(1);
449 writel(v, priv->mac_reg + EMAC_TX_CTL1);
450
451 v = readl(priv->mac_reg + EMAC_RX_CTL1);
452
453
454
455 v |= BIT(1);
456 writel(v, priv->mac_reg + EMAC_RX_CTL1);
457
458
459 writel(8 << 24, priv->mac_reg + EMAC_CTL1);
460
461
462 rx_descs_init(priv);
463 tx_descs_init(priv);
464
465
466 phy_startup(priv->phydev);
467
468 sun8i_adjust_link(priv, priv->phydev);
469
470
471 v = readl(priv->mac_reg + EMAC_RX_CTL1);
472 v |= BIT(30);
473 writel(v, priv->mac_reg + EMAC_RX_CTL1);
474
475 v = readl(priv->mac_reg + EMAC_TX_CTL1);
476 v |= BIT(30);
477 writel(v, priv->mac_reg + EMAC_TX_CTL1);
478
479
480 setbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
481 setbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
482
483 return 0;
484}
485
486static int parse_phy_pins(struct udevice *dev)
487{
488 struct emac_eth_dev *priv = dev_get_priv(dev);
489 int offset;
490 const char *pin_name;
491 int drive, pull = SUN4I_PINCTRL_NO_PULL, i;
492
493 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
494 "pinctrl-0");
495 if (offset < 0) {
496 printf("WARNING: emac: cannot find pinctrl-0 node\n");
497 return offset;
498 }
499
500 drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
501 "drive-strength", ~0);
502 if (drive != ~0) {
503 if (drive <= 10)
504 drive = SUN4I_PINCTRL_10_MA;
505 else if (drive <= 20)
506 drive = SUN4I_PINCTRL_20_MA;
507 else if (drive <= 30)
508 drive = SUN4I_PINCTRL_30_MA;
509 else
510 drive = SUN4I_PINCTRL_40_MA;
511 }
512
513 if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-up", NULL))
514 pull = SUN4I_PINCTRL_PULL_UP;
515 else if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-down", NULL))
516 pull = SUN4I_PINCTRL_PULL_DOWN;
517
518 for (i = 0; ; i++) {
519 int pin;
520
521 pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
522 "pins", i, NULL);
523 if (!pin_name)
524 break;
525
526 pin = sunxi_name_to_gpio(pin_name);
527 if (pin < 0)
528 continue;
529
530 if (priv->variant == H3_EMAC)
531 sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_H3);
532 else if (priv->variant == R40_GMAC)
533 sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_R40);
534 else
535 sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX);
536
537 if (drive != ~0)
538 sunxi_gpio_set_drv(pin, drive);
539 if (pull != ~0)
540 sunxi_gpio_set_pull(pin, pull);
541 }
542
543 if (!i) {
544 printf("WARNING: emac: cannot find pins property\n");
545 return -2;
546 }
547
548 return 0;
549}
550
551static int _sun8i_eth_recv(struct emac_eth_dev *priv, uchar **packetp)
552{
553 u32 status, desc_num = priv->rx_currdescnum;
554 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
555 int length = -EAGAIN;
556 int good_packet = 1;
557 uintptr_t desc_start = (uintptr_t)desc_p;
558 uintptr_t desc_end = desc_start +
559 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
560
561 ulong data_start = (uintptr_t)desc_p->buf_addr;
562 ulong data_end;
563
564
565 invalidate_dcache_range(desc_start, desc_end);
566
567 status = desc_p->status;
568
569
570 if (!(status & BIT(31))) {
571 length = (desc_p->status >> 16) & 0x3FFF;
572
573 if (length < 0x40) {
574 good_packet = 0;
575 debug("RX: Bad Packet (runt)\n");
576 }
577
578 data_end = data_start + length;
579
580 invalidate_dcache_range(rounddown(data_start,
581 ARCH_DMA_MINALIGN),
582 roundup(data_end,
583 ARCH_DMA_MINALIGN));
584 if (good_packet) {
585 if (length > CONFIG_ETH_RXSIZE) {
586 printf("Received packet is too big (len=%d)\n",
587 length);
588 return -EMSGSIZE;
589 }
590 *packetp = (uchar *)(ulong)desc_p->buf_addr;
591 return length;
592 }
593 }
594
595 return length;
596}
597
598static int _sun8i_emac_eth_send(struct emac_eth_dev *priv, void *packet,
599 int len)
600{
601 u32 v, desc_num = priv->tx_currdescnum;
602 struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num];
603 uintptr_t desc_start = (uintptr_t)desc_p;
604 uintptr_t desc_end = desc_start +
605 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
606
607 uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
608 uintptr_t data_end = data_start +
609 roundup(len, ARCH_DMA_MINALIGN);
610
611
612 invalidate_dcache_range(desc_start, desc_end);
613
614 desc_p->st = len;
615
616 desc_p->st |= BIT(24);
617
618 memcpy((void *)data_start, packet, len);
619
620
621 flush_dcache_range(data_start, data_end);
622
623
624 desc_p->st |= BIT(30);
625 desc_p->st |= BIT(31);
626
627
628 desc_p->st |= BIT(29);
629 desc_p->status = BIT(31);
630
631
632 flush_dcache_range(desc_start, desc_end);
633
634
635 if (++desc_num >= CONFIG_TX_DESCR_NUM)
636 desc_num = 0;
637 priv->tx_currdescnum = desc_num;
638
639
640 v = readl(priv->mac_reg + EMAC_TX_CTL1);
641 v |= BIT(31);
642 v |= BIT(30);
643 writel(v, priv->mac_reg + EMAC_TX_CTL1);
644
645 return 0;
646}
647
648static int sun8i_eth_write_hwaddr(struct udevice *dev)
649{
650 struct eth_pdata *pdata = dev_get_platdata(dev);
651 struct emac_eth_dev *priv = dev_get_priv(dev);
652
653 return _sun8i_write_hwaddr(priv, pdata->enetaddr);
654}
655
656static int sun8i_emac_board_setup(struct emac_eth_dev *priv)
657{
658 int ret;
659
660 ret = clk_enable(&priv->tx_clk);
661 if (ret) {
662 dev_err(dev, "failed to enable TX clock\n");
663 return ret;
664 }
665
666 if (reset_valid(&priv->tx_rst)) {
667 ret = reset_deassert(&priv->tx_rst);
668 if (ret) {
669 dev_err(dev, "failed to deassert TX reset\n");
670 goto err_tx_clk;
671 }
672 }
673
674
675 if (clk_valid(&priv->ephy_clk)) {
676 ret = clk_enable(&priv->ephy_clk);
677 if (ret) {
678 dev_err(dev, "failed to enable EPHY TX clock\n");
679 return ret;
680 }
681 }
682
683 if (reset_valid(&priv->ephy_rst)) {
684 ret = reset_deassert(&priv->ephy_rst);
685 if (ret) {
686 dev_err(dev, "failed to deassert EPHY TX clock\n");
687 return ret;
688 }
689 }
690
691 return 0;
692
693err_tx_clk:
694 clk_disable(&priv->tx_clk);
695 return ret;
696}
697
698#if defined(CONFIG_DM_GPIO)
699static int sun8i_mdio_reset(struct mii_dev *bus)
700{
701 struct udevice *dev = bus->priv;
702 struct emac_eth_dev *priv = dev_get_priv(dev);
703 struct sun8i_eth_pdata *pdata = dev_get_platdata(dev);
704 int ret;
705
706 if (!dm_gpio_is_valid(&priv->reset_gpio))
707 return 0;
708
709
710 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
711 if (ret)
712 return ret;
713
714 udelay(pdata->reset_delays[0]);
715
716 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
717 if (ret)
718 return ret;
719
720 udelay(pdata->reset_delays[1]);
721
722 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
723 if (ret)
724 return ret;
725
726 udelay(pdata->reset_delays[2]);
727
728 return 0;
729}
730#endif
731
732static int sun8i_mdio_init(const char *name, struct udevice *priv)
733{
734 struct mii_dev *bus = mdio_alloc();
735
736 if (!bus) {
737 debug("Failed to allocate MDIO bus\n");
738 return -ENOMEM;
739 }
740
741 bus->read = sun8i_mdio_read;
742 bus->write = sun8i_mdio_write;
743 snprintf(bus->name, sizeof(bus->name), name);
744 bus->priv = (void *)priv;
745#if defined(CONFIG_DM_GPIO)
746 bus->reset = sun8i_mdio_reset;
747#endif
748
749 return mdio_register(bus);
750}
751
752static int sun8i_emac_eth_start(struct udevice *dev)
753{
754 struct eth_pdata *pdata = dev_get_platdata(dev);
755
756 return _sun8i_emac_eth_init(dev->priv, pdata->enetaddr);
757}
758
759static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
760{
761 struct emac_eth_dev *priv = dev_get_priv(dev);
762
763 return _sun8i_emac_eth_send(priv, packet, length);
764}
765
766static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
767{
768 struct emac_eth_dev *priv = dev_get_priv(dev);
769
770 return _sun8i_eth_recv(priv, packetp);
771}
772
773static int _sun8i_free_pkt(struct emac_eth_dev *priv)
774{
775 u32 desc_num = priv->rx_currdescnum;
776 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
777 uintptr_t desc_start = (uintptr_t)desc_p;
778 uintptr_t desc_end = desc_start +
779 roundup(sizeof(u32), ARCH_DMA_MINALIGN);
780
781
782 desc_p->status |= BIT(31);
783
784
785 flush_dcache_range(desc_start, desc_end);
786
787
788 if (++desc_num >= CONFIG_RX_DESCR_NUM)
789 desc_num = 0;
790 priv->rx_currdescnum = desc_num;
791
792 return 0;
793}
794
795static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet,
796 int length)
797{
798 struct emac_eth_dev *priv = dev_get_priv(dev);
799
800 return _sun8i_free_pkt(priv);
801}
802
803static void sun8i_emac_eth_stop(struct udevice *dev)
804{
805 struct emac_eth_dev *priv = dev_get_priv(dev);
806
807
808 clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
809 clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
810
811
812 clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, BIT(30));
813
814 phy_shutdown(priv->phydev);
815}
816
817static int sun8i_emac_eth_probe(struct udevice *dev)
818{
819 struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
820 struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
821 struct emac_eth_dev *priv = dev_get_priv(dev);
822 int ret;
823
824 priv->mac_reg = (void *)pdata->iobase;
825
826 ret = sun8i_emac_board_setup(priv);
827 if (ret)
828 return ret;
829
830 sun8i_emac_set_syscon(sun8i_pdata, priv);
831
832 sun8i_mdio_init(dev->name, dev);
833 priv->bus = miiphy_get_dev_by_name(dev->name);
834
835 return sun8i_phy_init(priv, dev);
836}
837
838static const struct eth_ops sun8i_emac_eth_ops = {
839 .start = sun8i_emac_eth_start,
840 .write_hwaddr = sun8i_eth_write_hwaddr,
841 .send = sun8i_emac_eth_send,
842 .recv = sun8i_emac_eth_recv,
843 .free_pkt = sun8i_eth_free_pkt,
844 .stop = sun8i_emac_eth_stop,
845};
846
847static int sun8i_get_ephy_nodes(struct emac_eth_dev *priv)
848{
849 int emac_node, ephy_node, ret, ephy_handle;
850
851 emac_node = fdt_path_offset(gd->fdt_blob,
852 "/soc/ethernet@1c30000");
853 if (emac_node < 0) {
854 debug("failed to get emac node\n");
855 return emac_node;
856 }
857 ephy_handle = fdtdec_lookup_phandle(gd->fdt_blob,
858 emac_node, "phy-handle");
859
860
861 ephy_node = fdt_path_offset(gd->fdt_blob,
862 "/soc/ethernet@1c30000/mdio-mux/mdio@1/ethernet-phy@1");
863 if (ephy_node < 0) {
864 debug("failed to get mdio-mux with internal PHY\n");
865 return ephy_node;
866 }
867
868
869 if (ephy_node != ephy_handle)
870 return 0;
871
872 ret = fdt_node_check_compatible(gd->fdt_blob, ephy_node,
873 "allwinner,sun8i-h3-mdio-internal");
874 if (ret < 0) {
875 debug("failed to find mdio-internal node\n");
876 return ret;
877 }
878
879 ret = clk_get_by_index_nodev(offset_to_ofnode(ephy_node), 0,
880 &priv->ephy_clk);
881 if (ret) {
882 dev_err(dev, "failed to get EPHY TX clock\n");
883 return ret;
884 }
885
886 ret = reset_get_by_index_nodev(offset_to_ofnode(ephy_node), 0,
887 &priv->ephy_rst);
888 if (ret) {
889 dev_err(dev, "failed to get EPHY TX reset\n");
890 return ret;
891 }
892
893 priv->use_internal_phy = true;
894
895 return 0;
896}
897
898static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
899{
900 struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
901 struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
902 struct emac_eth_dev *priv = dev_get_priv(dev);
903 const char *phy_mode;
904 const fdt32_t *reg;
905 int node = dev_of_offset(dev);
906 int offset = 0;
907#ifdef CONFIG_DM_GPIO
908 int reset_flags = GPIOD_IS_OUT;
909#endif
910 int ret;
911
912 pdata->iobase = devfdt_get_addr(dev);
913 if (pdata->iobase == FDT_ADDR_T_NONE) {
914 debug("%s: Cannot find MAC base address\n", __func__);
915 return -EINVAL;
916 }
917
918 priv->variant = dev_get_driver_data(dev);
919
920 if (!priv->variant) {
921 printf("%s: Missing variant\n", __func__);
922 return -EINVAL;
923 }
924
925 ret = clk_get_by_name(dev, "stmmaceth", &priv->tx_clk);
926 if (ret) {
927 dev_err(dev, "failed to get TX clock\n");
928 return ret;
929 }
930
931 ret = reset_get_by_name(dev, "stmmaceth", &priv->tx_rst);
932 if (ret && ret != -ENOENT) {
933 dev_err(dev, "failed to get TX reset\n");
934 return ret;
935 }
936
937 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
938 if (offset < 0) {
939 debug("%s: cannot find syscon node\n", __func__);
940 return -EINVAL;
941 }
942
943 reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
944 if (!reg) {
945 debug("%s: cannot find reg property in syscon node\n",
946 __func__);
947 return -EINVAL;
948 }
949 priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
950 offset, reg);
951 if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
952 debug("%s: Cannot find syscon base address\n", __func__);
953 return -EINVAL;
954 }
955
956 pdata->phy_interface = -1;
957 priv->phyaddr = -1;
958 priv->use_internal_phy = false;
959
960 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
961 if (offset < 0) {
962 debug("%s: Cannot find PHY address\n", __func__);
963 return -EINVAL;
964 }
965 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
966
967 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
968
969 if (phy_mode)
970 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
971 printf("phy interface%d\n", pdata->phy_interface);
972
973 if (pdata->phy_interface == -1) {
974 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
975 return -EINVAL;
976 }
977
978 if (priv->variant == H3_EMAC) {
979 ret = sun8i_get_ephy_nodes(priv);
980 if (ret)
981 return ret;
982 }
983
984 priv->interface = pdata->phy_interface;
985
986 if (!priv->use_internal_phy)
987 parse_phy_pins(dev);
988
989 sun8i_pdata->tx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
990 "allwinner,tx-delay-ps", 0);
991 if (sun8i_pdata->tx_delay_ps < 0 || sun8i_pdata->tx_delay_ps > 700)
992 printf("%s: Invalid TX delay value %d\n", __func__,
993 sun8i_pdata->tx_delay_ps);
994
995 sun8i_pdata->rx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
996 "allwinner,rx-delay-ps", 0);
997 if (sun8i_pdata->rx_delay_ps < 0 || sun8i_pdata->rx_delay_ps > 3100)
998 printf("%s: Invalid RX delay value %d\n", __func__,
999 sun8i_pdata->rx_delay_ps);
1000
1001#ifdef CONFIG_DM_GPIO
1002 if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
1003 "snps,reset-active-low"))
1004 reset_flags |= GPIOD_ACTIVE_LOW;
1005
1006 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
1007 &priv->reset_gpio, reset_flags);
1008
1009 if (ret == 0) {
1010 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
1011 "snps,reset-delays-us",
1012 sun8i_pdata->reset_delays, 3);
1013 } else if (ret == -ENOENT) {
1014 ret = 0;
1015 }
1016#endif
1017
1018 return 0;
1019}
1020
1021static const struct udevice_id sun8i_emac_eth_ids[] = {
1022 {.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC },
1023 {.compatible = "allwinner,sun50i-a64-emac",
1024 .data = (uintptr_t)A64_EMAC },
1025 {.compatible = "allwinner,sun8i-a83t-emac",
1026 .data = (uintptr_t)A83T_EMAC },
1027 {.compatible = "allwinner,sun8i-r40-gmac",
1028 .data = (uintptr_t)R40_GMAC },
1029 { }
1030};
1031
1032U_BOOT_DRIVER(eth_sun8i_emac) = {
1033 .name = "eth_sun8i_emac",
1034 .id = UCLASS_ETH,
1035 .of_match = sun8i_emac_eth_ids,
1036 .ofdata_to_platdata = sun8i_emac_eth_ofdata_to_platdata,
1037 .probe = sun8i_emac_eth_probe,
1038 .ops = &sun8i_emac_eth_ops,
1039 .priv_auto_alloc_size = sizeof(struct emac_eth_dev),
1040 .platdata_auto_alloc_size = sizeof(struct sun8i_eth_pdata),
1041 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1042};
1043
