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17#ifndef __DRIVERS_USB_DWC3_CORE_H
18#define __DRIVERS_USB_DWC3_CORE_H
19
20#include <linux/ioport.h>
21
22#include <linux/usb/ch9.h>
23#include <linux/usb/otg.h>
24
25#define DWC3_MSG_MAX 500
26
27
28#define DWC3_EP0_BOUNCE_SIZE 512
29#define DWC3_ENDPOINTS_NUM 32
30#define DWC3_XHCI_RESOURCES_NUM 2
31
32#define DWC3_SCRATCHBUF_SIZE 4096
33#define DWC3_EVENT_SIZE 4
34#define DWC3_EVENT_MAX_NUM 64
35#define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM)
36#define DWC3_EVENT_TYPE_MASK 0xfe
37
38#define DWC3_EVENT_TYPE_DEV 0
39#define DWC3_EVENT_TYPE_CARKIT 3
40#define DWC3_EVENT_TYPE_I2C 4
41
42#define DWC3_DEVICE_EVENT_DISCONNECT 0
43#define DWC3_DEVICE_EVENT_RESET 1
44#define DWC3_DEVICE_EVENT_CONNECT_DONE 2
45#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
46#define DWC3_DEVICE_EVENT_WAKEUP 4
47#define DWC3_DEVICE_EVENT_HIBER_REQ 5
48#define DWC3_DEVICE_EVENT_EOPF 6
49#define DWC3_DEVICE_EVENT_SOF 7
50#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
51#define DWC3_DEVICE_EVENT_CMD_CMPL 10
52#define DWC3_DEVICE_EVENT_OVERFLOW 11
53
54#define DWC3_GEVNTCOUNT_MASK 0xfffc
55#define DWC3_GSNPSID_MASK 0xffff0000
56#define DWC3_GSNPSREV_MASK 0xffff
57
58
59#define DWC3_XHCI_REGS_START 0x0
60#define DWC3_XHCI_REGS_END 0x7fff
61#define DWC3_GLOBALS_REGS_START 0xc100
62#define DWC3_GLOBALS_REGS_END 0xc6ff
63#define DWC3_DEVICE_REGS_START 0xc700
64#define DWC3_DEVICE_REGS_END 0xcbff
65#define DWC3_OTG_REGS_START 0xcc00
66#define DWC3_OTG_REGS_END 0xccff
67
68
69#define DWC3_GSBUSCFG0 0xc100
70#define DWC3_GSBUSCFG1 0xc104
71#define DWC3_GTXTHRCFG 0xc108
72#define DWC3_GRXTHRCFG 0xc10c
73#define DWC3_GCTL 0xc110
74#define DWC3_GEVTEN 0xc114
75#define DWC3_GSTS 0xc118
76#define DWC3_GSNPSID 0xc120
77#define DWC3_GGPIO 0xc124
78#define DWC3_GUID 0xc128
79#define DWC3_GUCTL 0xc12c
80#define DWC3_GBUSERRADDR0 0xc130
81#define DWC3_GBUSERRADDR1 0xc134
82#define DWC3_GPRTBIMAP0 0xc138
83#define DWC3_GPRTBIMAP1 0xc13c
84#define DWC3_GHWPARAMS0 0xc140
85#define DWC3_GHWPARAMS1 0xc144
86#define DWC3_GHWPARAMS2 0xc148
87#define DWC3_GHWPARAMS3 0xc14c
88#define DWC3_GHWPARAMS4 0xc150
89#define DWC3_GHWPARAMS5 0xc154
90#define DWC3_GHWPARAMS6 0xc158
91#define DWC3_GHWPARAMS7 0xc15c
92#define DWC3_GDBGFIFOSPACE 0xc160
93#define DWC3_GDBGLTSSM 0xc164
94#define DWC3_GPRTBIMAP_HS0 0xc180
95#define DWC3_GPRTBIMAP_HS1 0xc184
96#define DWC3_GPRTBIMAP_FS0 0xc188
97#define DWC3_GPRTBIMAP_FS1 0xc18c
98
99#define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
100#define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04))
101
102#define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04))
103
104#define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))
105
106#define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04))
107#define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04))
108
109#define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10))
110#define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10))
111#define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10))
112#define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10))
113
114#define DWC3_GHWPARAMS8 0xc600
115
116
117#define DWC3_DCFG 0xc700
118#define DWC3_DCTL 0xc704
119#define DWC3_DEVTEN 0xc708
120#define DWC3_DSTS 0xc70c
121#define DWC3_DGCMDPAR 0xc710
122#define DWC3_DGCMD 0xc714
123#define DWC3_DALEPENA 0xc720
124#define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10))
125#define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10))
126#define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10))
127#define DWC3_DEPCMD(n) (0xc80c + (n * 0x10))
128
129
130#define DWC3_OCFG 0xcc00
131#define DWC3_OCTL 0xcc04
132#define DWC3_OEVT 0xcc08
133#define DWC3_OEVTEN 0xcc0C
134#define DWC3_OSTS 0xcc10
135
136
137
138
139#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
140#define DWC3_GCTL_U2RSTECN (1 << 16)
141#define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
142#define DWC3_GCTL_CLK_BUS (0)
143#define DWC3_GCTL_CLK_PIPE (1)
144#define DWC3_GCTL_CLK_PIPEHALF (2)
145#define DWC3_GCTL_CLK_MASK (3)
146
147#define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
148#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
149#define DWC3_GCTL_PRTCAP_HOST 1
150#define DWC3_GCTL_PRTCAP_DEVICE 2
151#define DWC3_GCTL_PRTCAP_OTG 3
152
153#define DWC3_GCTL_CORESOFTRESET (1 << 11)
154#define DWC3_GCTL_SOFITPSYNC (1 << 10)
155#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
156#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
157#define DWC3_GCTL_DISSCRAMBLE (1 << 3)
158#define DWC3_GCTL_U2EXIT_LFPS (1 << 2)
159#define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1)
160#define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
161
162
163#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
164#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
165
166
167#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
168#define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29)
169#define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24)
170#define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
171#define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
172#define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
173#define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18)
174#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
175#define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9)
176#define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8)
177#define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
178#define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
179
180
181#define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
182#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
183
184
185#define DWC3_GEVNTSIZ_INTMASK (1 << 31)
186#define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
187
188
189#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
190#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
191#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
192#define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
193#define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
194#define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
195
196
197#define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
198#define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
199#define DWC3_GHWPARAMS3_SSPHY_IFC_ENA 1
200#define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
201#define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
202#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
203#define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
204#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
205#define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
206#define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
207#define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
208
209
210#define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
211#define DWC3_MAX_HIBER_SCRATCHBUFS 15
212
213
214#define DWC3_GHWPARAMS6_EN_FPGA (1 << 7)
215
216
217#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
218#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
219
220#define DWC3_DCFG_SPEED_MASK (7 << 0)
221#define DWC3_DCFG_SUPERSPEED (4 << 0)
222#define DWC3_DCFG_HIGHSPEED (0 << 0)
223#define DWC3_DCFG_FULLSPEED2 (1 << 0)
224#define DWC3_DCFG_LOWSPEED (2 << 0)
225#define DWC3_DCFG_FULLSPEED1 (3 << 0)
226
227#define DWC3_DCFG_LPM_CAP (1 << 22)
228
229
230#define DWC3_DCTL_RUN_STOP (1 << 31)
231#define DWC3_DCTL_CSFTRST (1 << 30)
232#define DWC3_DCTL_LSFTRST (1 << 29)
233
234#define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
235#define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
236
237#define DWC3_DCTL_APPL1RES (1 << 23)
238
239
240#define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
241#define DWC3_DCTL_TRGTULST(n) ((n) << 17)
242#define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
243#define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
244#define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
245#define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
246#define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
247
248
249#define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf)
250#define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20)
251
252#define DWC3_DCTL_KEEP_CONNECT (1 << 19)
253#define DWC3_DCTL_L1_HIBER_EN (1 << 18)
254#define DWC3_DCTL_CRS (1 << 17)
255#define DWC3_DCTL_CSS (1 << 16)
256
257#define DWC3_DCTL_INITU2ENA (1 << 12)
258#define DWC3_DCTL_ACCEPTU2ENA (1 << 11)
259#define DWC3_DCTL_INITU1ENA (1 << 10)
260#define DWC3_DCTL_ACCEPTU1ENA (1 << 9)
261#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
262
263#define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
264#define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
265
266#define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
267#define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
268#define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
269#define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
270#define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
271#define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
272#define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
273
274
275#define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12)
276#define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11)
277#define DWC3_DEVTEN_CMDCMPLTEN (1 << 10)
278#define DWC3_DEVTEN_ERRTICERREN (1 << 9)
279#define DWC3_DEVTEN_SOFEN (1 << 7)
280#define DWC3_DEVTEN_EOPFEN (1 << 6)
281#define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5)
282#define DWC3_DEVTEN_WKUPEVTEN (1 << 4)
283#define DWC3_DEVTEN_ULSTCNGEN (1 << 3)
284#define DWC3_DEVTEN_CONNECTDONEEN (1 << 2)
285#define DWC3_DEVTEN_USBRSTEN (1 << 1)
286#define DWC3_DEVTEN_DISCONNEVTEN (1 << 0)
287
288
289#define DWC3_DSTS_DCNRD (1 << 29)
290
291
292#define DWC3_DSTS_PWRUPREQ (1 << 24)
293
294
295#define DWC3_DSTS_RSS (1 << 25)
296#define DWC3_DSTS_SSS (1 << 24)
297
298#define DWC3_DSTS_COREIDLE (1 << 23)
299#define DWC3_DSTS_DEVCTRLHLT (1 << 22)
300
301#define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
302#define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
303
304#define DWC3_DSTS_RXFIFOEMPTY (1 << 17)
305
306#define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
307#define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
308
309#define DWC3_DSTS_CONNECTSPD (7 << 0)
310
311#define DWC3_DSTS_SUPERSPEED (4 << 0)
312#define DWC3_DSTS_HIGHSPEED (0 << 0)
313#define DWC3_DSTS_FULLSPEED2 (1 << 0)
314#define DWC3_DSTS_LOWSPEED (2 << 0)
315#define DWC3_DSTS_FULLSPEED1 (3 << 0)
316
317
318#define DWC3_DGCMD_SET_LMP 0x01
319#define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
320#define DWC3_DGCMD_XMIT_FUNCTION 0x03
321
322
323#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
324#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
325
326#define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
327#define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
328#define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
329#define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
330
331#define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1)
332#define DWC3_DGCMD_CMDACT (1 << 10)
333#define DWC3_DGCMD_CMDIOC (1 << 8)
334
335
336#define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0)
337#define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
338#define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
339#define DWC3_DGCMDPAR_TX_FIFO (1 << 5)
340#define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
341#define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0)
342
343
344#define DWC3_DEPCMD_PARAM_SHIFT 16
345#define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
346#define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
347#define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1)
348#define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11)
349#define DWC3_DEPCMD_CMDACT (1 << 10)
350#define DWC3_DEPCMD_CMDIOC (1 << 8)
351
352#define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
353#define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
354#define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
355#define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
356#define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
357#define DWC3_DEPCMD_SETSTALL (0x04 << 0)
358
359#define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
360
361#define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
362#define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
363#define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
364
365
366#define DWC3_DALEPENA_EP(n) (1 << n)
367
368#define DWC3_DEPCMD_TYPE_CONTROL 0
369#define DWC3_DEPCMD_TYPE_ISOC 1
370#define DWC3_DEPCMD_TYPE_BULK 2
371#define DWC3_DEPCMD_TYPE_INTR 3
372
373
374
375struct dwc3_trb;
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387struct dwc3_event_buffer {
388 void *buf;
389 unsigned length;
390 unsigned int lpos;
391 unsigned int count;
392 unsigned int flags;
393
394#define DWC3_EVENT_PENDING (1UL << 0)
395
396 dma_addr_t dma;
397
398 struct dwc3 *dwc;
399};
400
401#define DWC3_EP_FLAG_STALLED (1 << 0)
402#define DWC3_EP_FLAG_WEDGED (1 << 1)
403
404#define DWC3_EP_DIRECTION_TX true
405#define DWC3_EP_DIRECTION_RX false
406
407#define DWC3_TRB_NUM 32
408#define DWC3_TRB_MASK (DWC3_TRB_NUM - 1)
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432struct dwc3_ep {
433 struct usb_ep endpoint;
434 struct list_head request_list;
435 struct list_head req_queued;
436
437 struct dwc3_trb *trb_pool;
438 dma_addr_t trb_pool_dma;
439 u32 free_slot;
440 u32 busy_slot;
441 const struct usb_ss_ep_comp_descriptor *comp_desc;
442 struct dwc3 *dwc;
443
444 u32 saved_state;
445 unsigned flags;
446#define DWC3_EP_ENABLED (1 << 0)
447#define DWC3_EP_STALL (1 << 1)
448#define DWC3_EP_WEDGE (1 << 2)
449#define DWC3_EP_BUSY (1 << 4)
450#define DWC3_EP_PENDING_REQUEST (1 << 5)
451#define DWC3_EP_MISSED_ISOC (1 << 6)
452
453
454#define DWC3_EP0_DIR_IN (1 << 31)
455
456 unsigned current_trb;
457
458 u8 number;
459 u8 type;
460 u8 resource_index;
461 u32 interval;
462
463 char name[20];
464
465 unsigned direction:1;
466 unsigned stream_capable:1;
467};
468
469enum dwc3_phy {
470 DWC3_PHY_UNKNOWN = 0,
471 DWC3_PHY_USB3,
472 DWC3_PHY_USB2,
473};
474
475enum dwc3_ep0_next {
476 DWC3_EP0_UNKNOWN = 0,
477 DWC3_EP0_COMPLETE,
478 DWC3_EP0_NRDY_DATA,
479 DWC3_EP0_NRDY_STATUS,
480};
481
482enum dwc3_ep0_state {
483 EP0_UNCONNECTED = 0,
484 EP0_SETUP_PHASE,
485 EP0_DATA_PHASE,
486 EP0_STATUS_PHASE,
487};
488
489enum dwc3_link_state {
490
491 DWC3_LINK_STATE_U0 = 0x00,
492 DWC3_LINK_STATE_U1 = 0x01,
493 DWC3_LINK_STATE_U2 = 0x02,
494 DWC3_LINK_STATE_U3 = 0x03,
495 DWC3_LINK_STATE_SS_DIS = 0x04,
496 DWC3_LINK_STATE_RX_DET = 0x05,
497 DWC3_LINK_STATE_SS_INACT = 0x06,
498 DWC3_LINK_STATE_POLL = 0x07,
499 DWC3_LINK_STATE_RECOV = 0x08,
500 DWC3_LINK_STATE_HRESET = 0x09,
501 DWC3_LINK_STATE_CMPLY = 0x0a,
502 DWC3_LINK_STATE_LPBK = 0x0b,
503 DWC3_LINK_STATE_RESET = 0x0e,
504 DWC3_LINK_STATE_RESUME = 0x0f,
505 DWC3_LINK_STATE_MASK = 0x0f,
506};
507
508
509#define DWC3_TRB_SIZE_MASK (0x00ffffff)
510#define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
511#define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
512#define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
513
514#define DWC3_TRBSTS_OK 0
515#define DWC3_TRBSTS_MISSED_ISOC 1
516#define DWC3_TRBSTS_SETUP_PENDING 2
517#define DWC3_TRB_STS_XFER_IN_PROG 4
518
519
520#define DWC3_TRB_CTRL_HWO (1 << 0)
521#define DWC3_TRB_CTRL_LST (1 << 1)
522#define DWC3_TRB_CTRL_CHN (1 << 2)
523#define DWC3_TRB_CTRL_CSP (1 << 3)
524#define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
525#define DWC3_TRB_CTRL_ISP_IMI (1 << 10)
526#define DWC3_TRB_CTRL_IOC (1 << 11)
527#define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
528
529#define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
530#define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
531#define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
532#define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
533#define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
534#define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
535#define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
536#define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
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544
545struct dwc3_trb {
546 u32 bpl;
547 u32 bph;
548 u32 size;
549 u32 ctrl;
550} __packed;
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564struct dwc3_hwparams {
565 u32 hwparams0;
566 u32 hwparams1;
567 u32 hwparams2;
568 u32 hwparams3;
569 u32 hwparams4;
570 u32 hwparams5;
571 u32 hwparams6;
572 u32 hwparams7;
573 u32 hwparams8;
574};
575
576
577#define DWC3_MODE(n) ((n) & 0x7)
578
579#define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
580
581
582#define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
583
584
585#define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
586#define DWC3_NUM_EPS_MASK (0x3f << 12)
587#define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
588 (DWC3_NUM_EPS_MASK)) >> 12)
589#define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
590 (DWC3_NUM_IN_EPS_MASK)) >> 18)
591
592
593#define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
594
595struct dwc3_request {
596 struct usb_request request;
597 struct list_head list;
598 struct dwc3_ep *dep;
599 u32 start_slot;
600
601 u8 epnum;
602 struct dwc3_trb *trb;
603 dma_addr_t trb_dma;
604
605 unsigned direction:1;
606 unsigned mapped:1;
607 unsigned queued:1;
608};
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613
614struct dwc3_scratchpad_array {
615 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
616};
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700struct dwc3 {
701 struct usb_ctrlrequest *ctrl_req;
702 struct dwc3_trb *ep0_trb;
703 void *ep0_bounce;
704 void *scratchbuf;
705 u8 *setup_buf;
706 dma_addr_t ctrl_req_addr;
707 dma_addr_t ep0_trb_addr;
708 dma_addr_t ep0_bounce_addr;
709 dma_addr_t scratch_addr;
710 struct dwc3_request ep0_usb_req;
711
712
713 spinlock_t lock;
714
715#if defined(__UBOOT__) && CONFIG_IS_ENABLED(DM_USB)
716 struct udevice *dev;
717#else
718 struct device *dev;
719#endif
720
721 struct platform_device *xhci;
722 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
723
724 struct dwc3_event_buffer **ev_buffs;
725 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
726
727 struct usb_gadget gadget;
728 struct usb_gadget_driver *gadget_driver;
729
730 void __iomem *regs;
731 size_t regs_size;
732
733 enum usb_dr_mode dr_mode;
734
735
736 u32 dcfg;
737 u32 gctl;
738
739 u32 nr_scratch;
740 u32 num_event_buffers;
741 u32 u1u2;
742 u32 maximum_speed;
743 u32 revision;
744
745#define DWC3_REVISION_173A 0x5533173a
746#define DWC3_REVISION_175A 0x5533175a
747#define DWC3_REVISION_180A 0x5533180a
748#define DWC3_REVISION_183A 0x5533183a
749#define DWC3_REVISION_185A 0x5533185a
750#define DWC3_REVISION_187A 0x5533187a
751#define DWC3_REVISION_188A 0x5533188a
752#define DWC3_REVISION_190A 0x5533190a
753#define DWC3_REVISION_194A 0x5533194a
754#define DWC3_REVISION_200A 0x5533200a
755#define DWC3_REVISION_202A 0x5533202a
756#define DWC3_REVISION_210A 0x5533210a
757#define DWC3_REVISION_220A 0x5533220a
758#define DWC3_REVISION_230A 0x5533230a
759#define DWC3_REVISION_240A 0x5533240a
760#define DWC3_REVISION_250A 0x5533250a
761#define DWC3_REVISION_260A 0x5533260a
762#define DWC3_REVISION_270A 0x5533270a
763#define DWC3_REVISION_280A 0x5533280a
764
765 enum dwc3_ep0_next ep0_next_event;
766 enum dwc3_ep0_state ep0state;
767 enum dwc3_link_state link_state;
768
769 u16 isoch_delay;
770 u16 u2sel;
771 u16 u2pel;
772 u8 u1sel;
773 u8 u1pel;
774
775 u8 speed;
776
777 u8 num_out_eps;
778 u8 num_in_eps;
779
780 void *mem;
781
782 struct dwc3_hwparams hwparams;
783 struct dentry *root;
784 struct debugfs_regset32 *regset;
785
786 u8 test_mode;
787 u8 test_mode_nr;
788 u8 lpm_nyet_threshold;
789 u8 hird_threshold;
790
791 unsigned delayed_status:1;
792 unsigned ep0_bounced:1;
793 unsigned ep0_expect_in:1;
794 unsigned has_hibernation:1;
795 unsigned has_lpm_erratum:1;
796 unsigned is_utmi_l1_suspend:1;
797 unsigned is_selfpowered:1;
798 unsigned is_fpga:1;
799 unsigned needs_fifo_resize:1;
800 unsigned pullups_connected:1;
801 unsigned resize_fifos:1;
802 unsigned setup_packet_pending:1;
803 unsigned start_config_issued:1;
804 unsigned three_stage_setup:1;
805
806 unsigned disable_scramble_quirk:1;
807 unsigned u2exit_lfps_quirk:1;
808 unsigned u2ss_inp3_quirk:1;
809 unsigned req_p1p2p3_quirk:1;
810 unsigned del_p1p2p3_quirk:1;
811 unsigned del_phy_power_chg_quirk:1;
812 unsigned lfps_filter_quirk:1;
813 unsigned rx_detect_poll_quirk:1;
814 unsigned dis_u3_susphy_quirk:1;
815 unsigned dis_u2_susphy_quirk:1;
816
817 unsigned tx_de_emphasis_quirk:1;
818 unsigned tx_de_emphasis:2;
819 int index;
820 struct list_head list;
821};
822
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825
826
827struct dwc3_event_type {
828 u32 is_devspec:1;
829 u32 type:7;
830 u32 reserved8_31:24;
831} __packed;
832
833#define DWC3_DEPEVT_XFERCOMPLETE 0x01
834#define DWC3_DEPEVT_XFERINPROGRESS 0x02
835#define DWC3_DEPEVT_XFERNOTREADY 0x03
836#define DWC3_DEPEVT_RXTXFIFOEVT 0x04
837#define DWC3_DEPEVT_STREAMEVT 0x06
838#define DWC3_DEPEVT_EPCMDCMPLT 0x07
839
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843
844static inline const char *dwc3_ep_event_string(u8 event)
845{
846 switch (event) {
847 case DWC3_DEPEVT_XFERCOMPLETE:
848 return "Transfer Complete";
849 case DWC3_DEPEVT_XFERINPROGRESS:
850 return "Transfer In-Progress";
851 case DWC3_DEPEVT_XFERNOTREADY:
852 return "Transfer Not Ready";
853 case DWC3_DEPEVT_RXTXFIFOEVT:
854 return "FIFO";
855 case DWC3_DEPEVT_STREAMEVT:
856 return "Stream";
857 case DWC3_DEPEVT_EPCMDCMPLT:
858 return "Endpoint Command Complete";
859 }
860
861 return "UNKNOWN";
862}
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883struct dwc3_event_depevt {
884 u32 one_bit:1;
885 u32 endpoint_number:5;
886 u32 endpoint_event:4;
887 u32 reserved11_10:2;
888 u32 status:4;
889
890
891#define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3)
892
893
894#define DEPEVT_STATUS_BUSERR (1 << 0)
895#define DEPEVT_STATUS_SHORT (1 << 1)
896#define DEPEVT_STATUS_IOC (1 << 2)
897#define DEPEVT_STATUS_LST (1 << 3)
898
899
900#define DEPEVT_STREAMEVT_FOUND 1
901#define DEPEVT_STREAMEVT_NOTFOUND 2
902
903
904#define DEPEVT_STATUS_CONTROL_DATA 1
905#define DEPEVT_STATUS_CONTROL_STATUS 2
906
907 u32 parameters:16;
908} __packed;
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932struct dwc3_event_devt {
933 u32 one_bit:1;
934 u32 device_event:7;
935 u32 type:4;
936 u32 reserved15_12:4;
937 u32 event_info:9;
938 u32 reserved31_25:7;
939} __packed;
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947
948struct dwc3_event_gevt {
949 u32 one_bit:1;
950 u32 device_event:7;
951 u32 phy_port_number:4;
952 u32 reserved31_12:20;
953} __packed;
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963union dwc3_event {
964 u32 raw;
965 struct dwc3_event_type type;
966 struct dwc3_event_depevt depevt;
967 struct dwc3_event_devt devt;
968 struct dwc3_event_gevt gevt;
969};
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978struct dwc3_gadget_ep_cmd_params {
979 u32 param2;
980 u32 param1;
981 u32 param0;
982};
983
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986
987
988#define DWC3_HAS_PERIPHERAL BIT(0)
989#define DWC3_HAS_XHCI BIT(1)
990#define DWC3_HAS_OTG BIT(3)
991
992
993int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc);
994int dwc3_init(struct dwc3 *dwc);
995void dwc3_remove(struct dwc3 *dwc);
996
997#ifdef CONFIG_USB_DWC3_HOST
998int dwc3_host_init(struct dwc3 *dwc);
999void dwc3_host_exit(struct dwc3 *dwc);
1000#else
1001static inline int dwc3_host_init(struct dwc3 *dwc)
1002{ return 0; }
1003static inline void dwc3_host_exit(struct dwc3 *dwc)
1004{ }
1005#endif
1006
1007#ifdef CONFIG_USB_DWC3_GADGET
1008int dwc3_gadget_init(struct dwc3 *dwc);
1009void dwc3_gadget_exit(struct dwc3 *dwc);
1010int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
1011int dwc3_gadget_get_link_state(struct dwc3 *dwc);
1012int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1013int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
1014 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params);
1015int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param);
1016#else
1017static inline int dwc3_gadget_init(struct dwc3 *dwc)
1018{ return 0; }
1019static inline void dwc3_gadget_exit(struct dwc3 *dwc)
1020{ }
1021static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
1022{ return 0; }
1023static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
1024{ return 0; }
1025static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
1026 enum dwc3_link_state state)
1027{ return 0; }
1028
1029static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
1030 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
1031{ return 0; }
1032static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
1033 int cmd, u32 param)
1034{ return 0; }
1035#endif
1036
1037#endif
1038