1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Configuation settings for the esd TASREG board. 4 * 5 * (C) Copyright 2004 6 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com 7 */ 8 9/* 10 * board/config.h - configuration options, board specific 11 */ 12 13#ifndef _M5249EVB_H 14#define _M5249EVB_H 15 16/* 17 * High Level Configuration Options 18 * (easy to change) 19 */ 20#define CONFIG_MCFTMR 21 22#define CONFIG_MCFUART 23#define CONFIG_SYS_UART_PORT (0) 24 25#undef CONFIG_WATCHDOG 26 27#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */ 28 29/* 30 * BOOTP options 31 */ 32#undef CONFIG_BOOTP_BOOTFILESIZE 33 34/* 35 * Command line configuration. 36 */ 37 38#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ 39 40#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ 41 42#define CONFIG_SYS_MEMTEST_START 0x400 43#define CONFIG_SYS_MEMTEST_END 0x380000 44 45/* 46 * Clock configuration: enable only one of the following options 47 */ 48 49#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ 50#define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */ 51#define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */ 52 53/* 54 * Low Level Configuration Settings 55 * (address mappings, register initial values, etc.) 56 * You should know what you are doing if you make changes here. 57 */ 58 59#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 60#define CONFIG_SYS_MBAR2 0x80000000 61 62/*----------------------------------------------------------------------- 63 * Definitions for initial stack pointer and data area (in DPRAM) 64 */ 65#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 66#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 67#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 68#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 69 70#define LDS_BOARD_TEXT \ 71 . = DEFINED(env_offset) ? env_offset : .; \ 72 env/embedded.o(.text); 73 74#define CONFIG_ENV_OFFSET 0x4000 /* Address of Environment Sector*/ 75#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ 76#define CONFIG_ENV_SECT_SIZE 0x2000 /* see README - env sector total size */ 77 78/*----------------------------------------------------------------------- 79 * Start addresses for the final memory configuration 80 * (Set up by the startup code) 81 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 82 */ 83#define CONFIG_SYS_SDRAM_BASE 0x00000000 84#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 85#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 86 87#if 0 /* test-only */ 88#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ 89#endif 90 91#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 92 93#define CONFIG_SYS_MONITOR_LEN 0x20000 94#define CONFIG_SYS_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */ 95#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 96 97/* 98 * For booting Linux, the board info and command line data 99 * have to be in the first 8 MB of memory, since this is 100 * the maximum mapped by the Linux kernel during initialization ?? 101 */ 102#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 103 104/*----------------------------------------------------------------------- 105 * FLASH organization 106 */ 107#ifdef CONFIG_SYS_FLASH_CFI 108 109# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 110# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 111# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 112# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 113# define CONFIG_SYS_FLASH_CHECKSUM 114# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 115#endif 116 117/*----------------------------------------------------------------------- 118 * Cache Configuration 119 */ 120#define CONFIG_SYS_CACHELINE_SIZE 16 121 122#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 123 CONFIG_SYS_INIT_RAM_SIZE - 8) 124#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 125 CONFIG_SYS_INIT_RAM_SIZE - 4) 126#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) 127#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ 128 CF_ADDRMASK(2) | \ 129 CF_ACR_EN | CF_ACR_SM_ALL) 130#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ 131 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 132 CF_ACR_EN | CF_ACR_SM_ALL) 133#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ 134 CF_CACR_DBWE) 135 136/*----------------------------------------------------------------------- 137 * Memory bank definitions 138 */ 139 140/* CS0 - AMD Flash, address 0xffc00000 */ 141#define CONFIG_SYS_CS0_BASE 0xffe00000 142#define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */ 143/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/ 144#define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ 145 146/* CS1 - FPGA, address 0xe0000000 */ 147#define CONFIG_SYS_CS1_BASE 0xe0000000 148#define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */ 149#define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ 150 151/*----------------------------------------------------------------------- 152 * Port configuration 153 */ 154#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ 155#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/ 156#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ 157#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ 158#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ 159#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ 160#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ 161 162#endif /* M5249 */ 163