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8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11
12
13
14#define CONFIG_E300 1
15
16#ifdef CONFIG_MMC
17#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
18#define CONFIG_SYS_FSL_ESDHC_USE_PIO
19#endif
20
21
22
23
24
25
26
27#define CONFIG_TSEC1
28#define CONFIG_VSC7385_ENET
29
30
31
32
33#define CONFIG_FSL_SERDES
34#define CONFIG_FSL_SERDES1 0xe3000
35
36
37
38
39#define CONFIG_SYS_SDRAM_BASE 0x00000000
40#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
41#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
42 | DDRCDR_PZ_LOZ \
43 | DDRCDR_NZ_LOZ \
44 | DDRCDR_ODT \
45 | DDRCDR_Q_DRN)
46
47
48
49
50
51
52#define CONFIG_SYS_DDR_SIZE 128
53
54#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
55#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
56 | CSCONFIG_ODT_RD_NEVER \
57 | CSCONFIG_ODT_WR_ONLY_CURRENT \
58 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
59
60#define CONFIG_SYS_DDR_TIMING_3 0x00000000
61#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
62 | (0 << TIMING_CFG0_WRT_SHIFT) \
63 | (0 << TIMING_CFG0_RRT_SHIFT) \
64 | (0 << TIMING_CFG0_WWT_SHIFT) \
65 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
66 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
67 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
68 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
69
70#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
71 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
72 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
73 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
74 | (6 << TIMING_CFG1_REFREC_SHIFT) \
75 | (2 << TIMING_CFG1_WRREC_SHIFT) \
76 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
77 | (2 << TIMING_CFG1_WRTORD_SHIFT))
78
79#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
80 | (4 << TIMING_CFG2_CPO_SHIFT) \
81 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
82 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
83 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
84 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
85 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
86
87#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
88 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
89
90#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
91 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
92 | SDRAM_CFG_DBW_32)
93
94
95#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
96#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
97 | (0x0232 << SDRAM_MODE_SD_SHIFT))
98
99#define CONFIG_SYS_DDR_MODE2 0x00000000
100
101
102
103
104#define CONFIG_SYS_MEMTEST_START 0x00001000
105#define CONFIG_SYS_MEMTEST_END 0x07f00000
106
107
108
109
110#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
111
112#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
113#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
114
115
116
117
118#define CONFIG_SYS_INIT_RAM_LOCK 1
119#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000
120#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
121#define CONFIG_SYS_GBL_DATA_OFFSET \
122 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
123
124
125
126
127#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
128
129#define CONFIG_SYS_FLASH_BASE 0xFE000000
130#define CONFIG_SYS_FLASH_SIZE 8
131
132
133#define CONFIG_SYS_MAX_FLASH_BANKS 1
134
135#define CONFIG_SYS_MAX_FLASH_SECT 135
136
137#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
138#define CONFIG_SYS_FLASH_WRITE_TOUT 500
139
140
141
142
143#define CONFIG_SYS_NAND_BASE 0xE0600000
144#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
145
146
147#ifdef CONFIG_VSC7385_ENET
148#define CONFIG_TSEC2
149
150#define CONFIG_SYS_VSC7385_BASE 0xF0000000
151#define CONFIG_SYS_VSC7385_SIZE (128 * 1024)
152
153
154#define CONFIG_VSC7385_IMAGE 0xFE7FE000
155#define CONFIG_VSC7385_IMAGE_SIZE 8192
156#endif
157
158
159
160#define CONFIG_SYS_NS16550_SERIAL
161#define CONFIG_SYS_NS16550_REG_SIZE 1
162#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
163
164#define CONFIG_SYS_BAUDRATE_TABLE \
165 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
166
167#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
168#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
169
170
171#define CONFIG_SYS_I2C
172#define CONFIG_SYS_I2C_FSL
173#define CONFIG_SYS_FSL_I2C_SPEED 400000
174#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
175#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
176#define CONFIG_SYS_FSL_I2C2_SPEED 400000
177#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
178#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
179#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
180
181
182
183
184
185
186
187#ifdef CONFIG_MPC8XXX_SPI
188#define CONFIG_USE_SPIFLASH
189#endif
190
191
192
193
194#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
195
196
197
198
199#define CONFIG_RTC_DS1337
200#define CONFIG_SYS_I2C_RTC_ADDR 0x68
201
202
203
204
205
206#define CONFIG_SYS_PCIE1_BASE 0xA0000000
207#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
208#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
209#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
210#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
211#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
212#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
213#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
214#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
215
216
217#define CONFIG_SYS_SCCR_PCIEXP1CM 1
218
219#define CONFIG_PCI_INDIRECT_BRIDGE
220#define CONFIG_PCIE
221
222#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957
223#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
224
225
226
227
228#define CONFIG_SYS_TSEC1_OFFSET 0x24000
229#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
230#define CONFIG_SYS_TSEC2_OFFSET 0x25000
231#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
232
233
234
235
236#define CONFIG_TSEC1_NAME "eTSEC0"
237#define CONFIG_TSEC2_NAME "eTSEC1"
238#define TSEC1_PHY_ADDR 2
239#define TSEC2_PHY_ADDR 1
240#define TSEC1_PHYIDX 0
241#define TSEC2_PHYIDX 0
242#define TSEC1_FLAGS TSEC_GIGABIT
243#define TSEC2_FLAGS TSEC_GIGABIT
244
245
246#define CONFIG_ETHPRIME "eTSEC0"
247
248
249
250
251#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
252 CONFIG_SYS_MONITOR_LEN)
253#define CONFIG_ENV_SECT_SIZE 0x10000
254#define CONFIG_ENV_SIZE 0x2000
255#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
256#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
257
258#define CONFIG_LOADS_ECHO 1
259#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
260
261
262
263
264#define CONFIG_BOOTP_BOOTFILESIZE
265
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267
268
269
270
271
272
273#define CONFIG_SYS_LOAD_ADDR 0x2000000
274
275#define CONFIG_SYS_CBSIZE 1024
276
277
278#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
279
280
281
282
283
284
285#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
286#define CONFIG_SYS_BOOTM_LEN (64 << 20)
287
288
289
290
291
292#define CONFIG_ENV_OVERWRITE
293
294#if defined(CONFIG_TSEC_ENET)
295#define CONFIG_HAS_ETH0
296#define CONFIG_HAS_ETH1
297#endif
298
299#define CONFIG_LOADADDR 800000
300
301
302#define CONFIG_EXTRA_ENV_SETTINGS \
303 "netdev=eth0\0" \
304 "consoledev=ttyS0\0" \
305 "nfsargs=setenv bootargs root=/dev/nfs rw " \
306 "nfsroot=${serverip}:${rootpath}\0" \
307 "ramargs=setenv bootargs root=/dev/ram rw\0" \
308 "addip=setenv bootargs ${bootargs} " \
309 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
310 ":${hostname}:${netdev}:off panic=1\0" \
311 "addtty=setenv bootargs ${bootargs}" \
312 " console=${consoledev},${baudrate}\0" \
313 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
314 "addmisc=setenv bootargs ${bootargs}\0" \
315 "kernel_addr=FE080000\0" \
316 "fdt_addr=FE280000\0" \
317 "ramdisk_addr=FE290000\0" \
318 "u-boot=mpc8308rdb/u-boot.bin\0" \
319 "kernel_addr_r=1000000\0" \
320 "fdt_addr_r=C00000\0" \
321 "hostname=mpc8308rdb\0" \
322 "bootfile=mpc8308rdb/uImage\0" \
323 "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \
324 "rootpath=/opt/eldk-4.2/ppc_6xx\0" \
325 "flash_self=run ramargs addip addtty addmtd addmisc;" \
326 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
327 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
328 "bootm ${kernel_addr} - ${fdt_addr}\0" \
329 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
330 "tftp ${fdt_addr_r} ${fdtfile};" \
331 "run nfsargs addip addtty addmtd addmisc;" \
332 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
333 "bootcmd=run flash_self\0" \
334 "load=tftp ${loadaddr} ${u-boot}\0" \
335 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
336 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
337 " +${filesize};cp.b ${fileaddr} " \
338 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
339 "upd=run load update\0" \
340
341#endif
342