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8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12
13
14
15#define CONFIG_E300 1
16
17#ifndef CONFIG_SYS_MONITOR_BASE
18#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
19#endif
20
21#define CONFIG_PCI_INDIRECT_BRIDGE
22#define CONFIG_FSL_ELBC 1
23
24
25
26
27
28
29
30#define CONFIG_VSC7385_ENET
31#define CONFIG_TSEC2
32
33#define CONFIG_SYS_MEMTEST_START 0x00001000
34#define CONFIG_SYS_MEMTEST_END 0x07f00000
35
36
37
38
39
40#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
41
42
43
44
45
46
47
48#ifdef CONFIG_VSC7385_ENET
49
50#define CONFIG_TSEC1
51
52
53#define CONFIG_VSC7385_IMAGE 0xFE7FE000
54#define CONFIG_VSC7385_IMAGE_SIZE 8192
55
56#endif
57
58
59
60
61#define CONFIG_SYS_SDRAM_BASE 0x00000000
62
63
64
65
66
67#define CONFIG_SYS_DDR_SIZE 128
68#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
69 | CSCONFIG_ODT_RD_NEVER \
70 | CSCONFIG_ODT_WR_ONLY_CURRENT \
71 | CSCONFIG_ROW_BIT_13 \
72 | CSCONFIG_COL_BIT_10)
73
74
75#define CONFIG_SYS_DDR_TIMING_3 0x00000000
76#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
77 | (0 << TIMING_CFG0_WRT_SHIFT) \
78 | (0 << TIMING_CFG0_RRT_SHIFT) \
79 | (0 << TIMING_CFG0_WWT_SHIFT) \
80 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
81 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
82 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
83 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
84
85#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
86 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
87 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
88 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
89 | (10 << TIMING_CFG1_REFREC_SHIFT) \
90 | (3 << TIMING_CFG1_WRREC_SHIFT) \
91 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
92 | (2 << TIMING_CFG1_WRTORD_SHIFT))
93
94#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
95 | (5 << TIMING_CFG2_CPO_SHIFT) \
96 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
97 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
98 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
99 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
100 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
101
102#define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
103 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
104
105#if defined(CONFIG_DDR_2T_TIMING)
106#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
107 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
108 | SDRAM_CFG_DBW_32 \
109 | SDRAM_CFG_2T_EN)
110
111#else
112#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
113 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
114 | SDRAM_CFG_DBW_32)
115
116#endif
117#define CONFIG_SYS_SDRAM_CFG2 0x00401000
118
119#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
120 | (0x0632 << SDRAM_MODE_SD_SHIFT))
121
122#define CONFIG_SYS_DDR_MODE_2 0x8000C000
123
124#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
125
126#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
127 | DDRCDR_PZ_NOMZ \
128 | DDRCDR_NZ_NOMZ \
129 | DDRCDR_M_ODR)
130
131
132
133
134#define CONFIG_SYS_FLASH_BASE 0xFE000000
135#define CONFIG_SYS_FLASH_SIZE 8
136#define CONFIG_SYS_FLASH_PROTECTION 1
137#define CONFIG_SYS_FLASH_EMPTY_INFO
138
139#define CONFIG_SYS_MAX_FLASH_BANKS 1
140#define CONFIG_SYS_MAX_FLASH_SECT 135
141
142#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
143#define CONFIG_SYS_FLASH_WRITE_TOUT 500
144
145#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
146 !defined(CONFIG_SPL_BUILD)
147#define CONFIG_SYS_RAMBOOT
148#endif
149
150#define CONFIG_SYS_INIT_RAM_LOCK 1
151#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
152#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
153
154#define CONFIG_SYS_GBL_DATA_OFFSET \
155 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
156#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
157
158
159#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
160#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
161
162
163#define CONFIG_SYS_NAND_BASE 0xE2800000
164
165#define CONFIG_MTD_PARTITION
166
167#define CONFIG_SYS_MAX_NAND_DEVICE 1
168#define CONFIG_NAND_FSL_ELBC 1
169#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
170#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
171
172
173#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
174#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
175
176
177#define CONFIG_SYS_BCSR_ADDR 0xFA000000
178#define CONFIG_SYS_BCSR_SIZE (32 * 1024)
179
180
181
182#ifdef CONFIG_VSC7385_ENET
183
184
185#define CONFIG_SYS_VSC7385_BASE 0xF0000000
186#define CONFIG_SYS_VSC7385_SIZE (128 * 1024)
187
188
189#endif
190
191#define CONFIG_MPC83XX_GPIO 1
192
193
194
195
196#define CONFIG_SYS_NS16550_SERIAL
197#define CONFIG_SYS_NS16550_REG_SIZE 1
198
199#define CONFIG_SYS_BAUDRATE_TABLE \
200 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
201
202#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
203#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
204
205
206#define CONFIG_SYS_I2C
207#define CONFIG_SYS_I2C_FSL
208#define CONFIG_SYS_FSL_I2C_SPEED 400000
209#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
210#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
211#define CONFIG_SYS_FSL_I2C2_SPEED 400000
212#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
213#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
214#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
215
216
217
218
219
220#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
221#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
222#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
223#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
224#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
225#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
226#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
227#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
228#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000
229
230#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057
231
232
233
234
235
236#define CONFIG_GMII
237
238#ifdef CONFIG_TSEC1
239#define CONFIG_HAS_ETH0
240#define CONFIG_TSEC1_NAME "TSEC0"
241#define CONFIG_SYS_TSEC1_OFFSET 0x24000
242#define TSEC1_PHY_ADDR 0x1c
243#define TSEC1_FLAGS TSEC_GIGABIT
244#define TSEC1_PHYIDX 0
245#endif
246
247#ifdef CONFIG_TSEC2
248#define CONFIG_HAS_ETH1
249#define CONFIG_TSEC2_NAME "TSEC1"
250#define CONFIG_SYS_TSEC2_OFFSET 0x25000
251#define TSEC2_PHY_ADDR 4
252#define TSEC2_FLAGS TSEC_GIGABIT
253#define TSEC2_PHYIDX 0
254#endif
255
256
257#define CONFIG_ETHPRIME "TSEC1"
258
259
260
261
262#define CONFIG_RTC_DS1337
263#define CONFIG_SYS_I2C_RTC_ADDR 0x68
264
265
266
267
268#if !defined(CONFIG_SYS_RAMBOOT)
269 #define CONFIG_ENV_ADDR \
270 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
271 #define CONFIG_ENV_SECT_SIZE 0x10000
272 #define CONFIG_ENV_SIZE 0x2000
273
274
275#else
276 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
277 #define CONFIG_ENV_SIZE 0x2000
278#endif
279
280#define CONFIG_LOADS_ECHO 1
281#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
282
283
284
285
286#define CONFIG_BOOTP_BOOTFILESIZE
287
288
289
290
291
292
293
294
295#define CONFIG_SYS_LOAD_ADDR 0x2000000
296#define CONFIG_SYS_CBSIZE 1024
297
298
299#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
300
301
302
303
304
305
306
307#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
308#define CONFIG_SYS_BOOTM_LEN (64 << 20)
309
310#define CONFIG_SYS_RCWH_PCIHOST 0x80000000
311
312#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
313
314
315#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2)
316
317#define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
318
319
320
321
322#define CONFIG_ENV_OVERWRITE
323
324#define CONFIG_NETDEV "eth1"
325
326#define CONFIG_HOSTNAME "mpc8313erdb"
327#define CONFIG_ROOTPATH "/nfs/root/path"
328#define CONFIG_BOOTFILE "uImage"
329
330#define CONFIG_UBOOTPATH "u-boot.bin"
331#define CONFIG_FDTFILE "mpc8313erdb.dtb"
332
333
334#define CONFIG_LOADADDR 800000
335
336#define CONFIG_EXTRA_ENV_SETTINGS \
337 "netdev=" CONFIG_NETDEV "\0" \
338 "ethprime=TSEC1\0" \
339 "uboot=" CONFIG_UBOOTPATH "\0" \
340 "tftpflash=tftpboot $loadaddr $uboot; " \
341 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
342 " +$filesize; " \
343 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
344 " +$filesize; " \
345 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
346 " $filesize; " \
347 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
348 " +$filesize; " \
349 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
350 " $filesize\0" \
351 "fdtaddr=780000\0" \
352 "fdtfile=" CONFIG_FDTFILE "\0" \
353 "console=ttyS0\0" \
354 "setbootargs=setenv bootargs " \
355 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
356 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
357 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
358 "$netdev:off " \
359 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
360
361#define CONFIG_NFSBOOTCOMMAND \
362 "setenv rootdev /dev/nfs;" \
363 "run setbootargs;" \
364 "run setipargs;" \
365 "tftp $loadaddr $bootfile;" \
366 "tftp $fdtaddr $fdtfile;" \
367 "bootm $loadaddr - $fdtaddr"
368
369#define CONFIG_RAMBOOTCOMMAND \
370 "setenv rootdev /dev/ram;" \
371 "run setbootargs;" \
372 "tftp $ramdiskaddr $ramdiskfile;" \
373 "tftp $loadaddr $bootfile;" \
374 "tftp $fdtaddr $fdtfile;" \
375 "bootm $loadaddr $ramdiskaddr $fdtaddr"
376
377#endif
378