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10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#define CONFIG_PCI1 1
14#define CONFIG_PCIE1 1
15#define CONFIG_PCIE2 1
16#define CONFIG_PCIE3 1
17#define CONFIG_FSL_PCI_INIT 1
18#define CONFIG_PCI_INDIRECT_BRIDGE 1
19#define CONFIG_SYS_PCI_64BIT 1
20
21#define CONFIG_ENV_OVERWRITE
22#define CONFIG_INTERRUPTS
23
24#ifndef __ASSEMBLY__
25extern unsigned long get_board_sys_clk(unsigned long dummy);
26#endif
27#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
28
29
30
31
32#define CONFIG_L2_CACHE
33#define CONFIG_BTB
34
35
36
37
38#define CONFIG_ENABLE_36BIT_PHYS 1
39
40#define CONFIG_SYS_MEMTEST_START 0x00200000
41#define CONFIG_SYS_MEMTEST_END 0x00400000
42
43#define CONFIG_SYS_CCSRBAR 0xe0000000
44#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
45
46
47#define CONFIG_SPD_EEPROM
48#define CONFIG_DDR_SPD
49
50#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
51#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
52
53#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
54#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
55#define CONFIG_VERY_BIG_RAM
56
57#define CONFIG_DIMM_SLOTS_PER_CTLR 1
58#define CONFIG_CHIP_SELECTS_PER_CTRL 2
59
60
61#define SPD_EEPROM_ADDRESS 0x51
62
63
64#ifndef CONFIG_SPD_EEPROM
65#error ("CONFIG_SPD_EEPROM is required")
66#endif
67
68#undef CONFIG_CLOCKS_IN_MHZ
69
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97
98#define CONFIG_SYS_BOOT_BLOCK 0xfc000000
99
100#define CONFIG_SYS_FLASH_BASE 0xff800000
101
102#define CONFIG_SYS_BR0_PRELIM 0xff801001
103#define CONFIG_SYS_BR1_PRELIM 0xfe801001
104
105#define CONFIG_SYS_OR0_PRELIM 0xff806e65
106#define CONFIG_SYS_OR1_PRELIM 0xff806e65
107
108#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
109
110#define CONFIG_SYS_FLASH_QUIET_TEST
111#define CONFIG_SYS_MAX_FLASH_BANKS 1
112#define CONFIG_SYS_MAX_FLASH_SECT 128
113#undef CONFIG_SYS_FLASH_CHECKSUM
114#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
115#define CONFIG_SYS_FLASH_WRITE_TOUT 500
116#define CONFIG_FLASH_SHOW_PROGRESS 45
117
118#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
119
120#define CONFIG_SYS_FLASH_EMPTY_INFO
121
122#define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000
123
124#define CONFIG_SYS_BR2_PRELIM 0xf8201001
125#define CONFIG_SYS_OR2_PRELIM 0xfff06ff7
126
127#define CONFIG_SYS_BR3_PRELIM 0xf8100801
128#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7
129
130#define CONFIG_FSL_PIXIS 1
131#define PIXIS_BASE 0xf8100000
132#define PIXIS_ID 0x0
133#define PIXIS_VER 0x1
134#define PIXIS_PVER 0x2
135#define PIXIS_RST 0x4
136#define PIXIS_AUX 0x6
137
138#define PIXIS_SPD 0x7
139#define PIXIS_VCTL 0x10
140#define PIXIS_VCFGEN0 0x12
141#define PIXIS_VCFGEN1 0x13
142#define PIXIS_VBOOT 0x16
143#define PIXIS_VBOOT_FMAP 0x80
144#define PIXIS_VBOOT_FBANK 0x40
145#define PIXIS_VSPEED0 0x17
146#define PIXIS_VSPEED1 0x18
147#define PIXIS_VCLKH 0x19
148#define PIXIS_VCLKL 0x1A
149#define PIXIS_VSPEED2 0x1d
150#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40
151#define PIXIS_VSPEED2_TSEC1SER 0x2
152#define PIXIS_VSPEED2_TSEC3SER 0x1
153#define PIXIS_VCFGEN1_TSEC1SER 0x20
154#define PIXIS_VCFGEN1_TSEC3SER 0x40
155#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
156#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
157
158#define CONFIG_SYS_INIT_RAM_LOCK 1
159#define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000
160#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
161
162#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
163#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
164
165#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
166#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
167
168
169
170
171
172#define CONFIG_SYS_NS16550_SERIAL
173#define CONFIG_SYS_NS16550_REG_SIZE 1
174#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
175
176#define CONFIG_SYS_BAUDRATE_TABLE \
177 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
178
179#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
180#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
181
182
183#define CONFIG_SYS_I2C
184#define CONFIG_SYS_I2C_FSL
185#define CONFIG_SYS_FSL_I2C_SPEED 400000
186#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
187#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
188#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
189#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
190
191
192
193
194
195#define CONFIG_SYS_PCIE_VIRT 0x80000000
196#define CONFIG_SYS_PCIE_PHYS 0x80000000
197#define CONFIG_SYS_PCI_VIRT 0xc0000000
198#define CONFIG_SYS_PCI_PHYS 0xc0000000
199
200#define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000
201#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
202#define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000
203#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000
204#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
205#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
206#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
207#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000
208
209
210#define CONFIG_SYS_PCIE2_NAME "Slot 1"
211#define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000
212#define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000
213#define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000
214#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000
215#define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000
216#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
217#define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000
218#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
219
220
221#define CONFIG_SYS_PCIE1_NAME "Slot 2"
222#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
223#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
224#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
225#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
226#define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000
227#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
228#define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000
229#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
230
231
232#define CONFIG_SYS_PCIE3_NAME "ULI"
233#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
234#define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000
235#define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000
236#define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000
237#define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000
238#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
239#define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000
240#define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000
241#define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000
242#define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000
243#define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000
244#define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000
245
246#if defined(CONFIG_PCI)
247
248
249#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
250
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252
253
254
255
256#if defined(CONFIG_VIDEO)
257#define CONFIG_BIOSEMU
258#define CONFIG_ATI_RADEON_FB
259#define CONFIG_VIDEO_LOGO
260#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
261#endif
262
263#undef CONFIG_EEPRO100
264#undef CONFIG_TULIP
265
266#ifndef CONFIG_PCI_PNP
267 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
268 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
269 #define PCI_IDSEL_NUMBER 0x11
270#endif
271
272#define CONFIG_PCI_SCAN_SHOW
273
274#ifdef CONFIG_SCSI_AHCI
275#define CONFIG_SATA_ULI5288
276#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
277#define CONFIG_SYS_SCSI_MAX_LUN 1
278#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
279#endif
280
281#endif
282
283#if defined(CONFIG_TSEC_ENET)
284
285#define CONFIG_MII_DEFAULT_TSEC 1
286#define CONFIG_TSEC1 1
287#define CONFIG_TSEC1_NAME "eTSEC1"
288#define CONFIG_TSEC3 1
289#define CONFIG_TSEC3_NAME "eTSEC3"
290
291#define CONFIG_PIXIS_SGMII_CMD
292#define CONFIG_FSL_SGMII_RISER 1
293#define SGMII_RISER_PHY_OFFSET 0x1c
294
295#define TSEC1_PHY_ADDR 0
296#define TSEC3_PHY_ADDR 1
297
298#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
299#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
300
301#define TSEC1_PHYIDX 0
302#define TSEC3_PHYIDX 0
303
304#define CONFIG_ETHPRIME "eTSEC1"
305#endif
306
307
308
309
310#define CONFIG_ENV_SECT_SIZE 0x10000
311#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
312#define CONFIG_ENV_ADDR 0xfff80000
313#else
314#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
315#endif
316#define CONFIG_ENV_SIZE 0x2000
317
318#define CONFIG_LOADS_ECHO 1
319#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
320
321
322
323
324#define CONFIG_BOOTP_BOOTFILESIZE
325
326
327
328
329
330#ifdef CONFIG_USB_EHCI_HCD
331#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
332#define CONFIG_PCI_EHCI_DEVICE 0
333#endif
334
335#undef CONFIG_WATCHDOG
336
337
338
339
340#define CONFIG_SYS_LOAD_ADDR 0x2000000
341
342
343
344
345
346
347#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
348#define CONFIG_SYS_BOOTM_LEN (64 << 20)
349
350#if defined(CONFIG_CMD_KGDB)
351#define CONFIG_KGDB_BAUDRATE 230400
352#endif
353
354
355
356
357
358
359#if defined(CONFIG_TSEC_ENET)
360#define CONFIG_HAS_ETH0
361#define CONFIG_HAS_ETH1
362#endif
363
364#define CONFIG_IPADDR 192.168.1.251
365
366#define CONFIG_HOSTNAME "8544ds_unknown"
367#define CONFIG_ROOTPATH "/nfs/mpc85xx"
368#define CONFIG_BOOTFILE "8544ds/uImage.uboot"
369#define CONFIG_UBOOTPATH 8544ds/u-boot.bin
370
371#define CONFIG_SERVERIP 192.168.1.1
372#define CONFIG_GATEWAYIP 192.168.1.1
373#define CONFIG_NETMASK 255.255.0.0
374
375#define CONFIG_LOADADDR 1000000
376
377#define CONFIG_EXTRA_ENV_SETTINGS \
378"netdev=eth0\0" \
379"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
380"tftpflash=tftpboot $loadaddr $uboot; " \
381 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
382 " +$filesize; " \
383 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
384 " +$filesize; " \
385 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
386 " $filesize; " \
387 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
388 " +$filesize; " \
389 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
390 " $filesize\0" \
391"consoledev=ttyS0\0" \
392"ramdiskaddr=2000000\0" \
393"ramdiskfile=8544ds/ramdisk.uboot\0" \
394"fdtaddr=1e00000\0" \
395"fdtfile=8544ds/mpc8544ds.dtb\0" \
396"bdev=sda3\0"
397
398#define CONFIG_NFSBOOTCOMMAND \
399 "setenv bootargs root=/dev/nfs rw " \
400 "nfsroot=$serverip:$rootpath " \
401 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
402 "console=$consoledev,$baudrate $othbootargs;" \
403 "tftp $loadaddr $bootfile;" \
404 "tftp $fdtaddr $fdtfile;" \
405 "bootm $loadaddr - $fdtaddr"
406
407#define CONFIG_RAMBOOTCOMMAND \
408 "setenv bootargs root=/dev/ram rw " \
409 "console=$consoledev,$baudrate $othbootargs;" \
410 "tftp $ramdiskaddr $ramdiskfile;" \
411 "tftp $loadaddr $bootfile;" \
412 "tftp $fdtaddr $fdtfile;" \
413 "bootm $loadaddr $ramdiskaddr $fdtaddr"
414
415#define CONFIG_BOOTCOMMAND \
416 "setenv bootargs root=/dev/$bdev rw " \
417 "console=$consoledev,$baudrate $othbootargs;" \
418 "tftp $loadaddr $bootfile;" \
419 "tftp $fdtaddr $fdtfile;" \
420 "bootm $loadaddr - $fdtaddr"
421
422#endif
423