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10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#ifdef CONFIG_RAMBOOT_PBL
14#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
15#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
16#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
17#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
18#endif
19
20#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
21
22#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
23#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
24 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
25#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
26#endif
27
28
29#define CONFIG_SYS_BOOK3E_HV
30
31#ifndef CONFIG_RESET_VECTOR_ADDRESS
32#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
33#endif
34
35#define CONFIG_SYS_FSL_CPC
36#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
37#define CONFIG_PCIE1
38#define CONFIG_PCIE2
39#define CONFIG_PCIE3
40#define CONFIG_SYS_PCI_64BIT
41
42#define CONFIG_SYS_SRIO
43#define CONFIG_SRIO1
44#define CONFIG_SRIO2
45#define CONFIG_SRIO_PCIE_BOOT_MASTER
46#define CONFIG_SYS_DPAA_RMAN
47
48#define CONFIG_ENV_OVERWRITE
49
50#if defined(CONFIG_SPIFLASH)
51 #define CONFIG_ENV_SIZE 0x2000
52 #define CONFIG_ENV_OFFSET 0x100000
53 #define CONFIG_ENV_SECT_SIZE 0x10000
54#elif defined(CONFIG_SDCARD)
55 #define CONFIG_FSL_FIXED_MMC_LOCATION
56 #define CONFIG_SYS_MMC_ENV_DEV 0
57 #define CONFIG_ENV_SIZE 0x2000
58 #define CONFIG_ENV_OFFSET (512 * 1658)
59#elif defined(CONFIG_NAND)
60#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
61#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
62#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
63#define CONFIG_ENV_ADDR 0xffe20000
64#define CONFIG_ENV_SIZE 0x2000
65#elif defined(CONFIG_ENV_IS_NOWHERE)
66#define CONFIG_ENV_SIZE 0x2000
67#else
68 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
69 - CONFIG_ENV_SECT_SIZE)
70 #define CONFIG_ENV_SIZE 0x2000
71 #define CONFIG_ENV_SECT_SIZE 0x20000
72#endif
73
74#ifndef __ASSEMBLY__
75unsigned long get_board_sys_clk(unsigned long dummy);
76#endif
77#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
78
79
80
81
82#define CONFIG_SYS_CACHE_STASHING
83#define CONFIG_BACKSIDE_L2_CACHE
84#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
85#define CONFIG_BTB
86
87#define CONFIG_ENABLE_36BIT_PHYS
88
89#ifdef CONFIG_PHYS_64BIT
90#define CONFIG_ADDR_MAP
91#define CONFIG_SYS_NUM_ADDR_MAP 64
92#endif
93
94#define CONFIG_POST CONFIG_SYS_POST_MEMORY
95#define CONFIG_SYS_MEMTEST_START 0x00200000
96#define CONFIG_SYS_MEMTEST_END 0x00400000
97
98
99
100
101#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
102#ifdef CONFIG_PHYS_64BIT
103#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
104 CONFIG_RAMBOOT_TEXT_BASE)
105#else
106#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
107#endif
108#define CONFIG_SYS_L3_SIZE (1024 << 10)
109#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
110
111#ifdef CONFIG_PHYS_64BIT
112#define CONFIG_SYS_DCSRBAR 0xf0000000
113#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
114#endif
115
116
117#define CONFIG_ID_EEPROM
118#define CONFIG_SYS_I2C_EEPROM_NXID
119#define CONFIG_SYS_EEPROM_BUS_NUM 0
120#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
121#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
122
123
124
125
126#define CONFIG_VERY_BIG_RAM
127#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
128#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
129
130#define CONFIG_DIMM_SLOTS_PER_CTLR 1
131#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
132
133#define CONFIG_DDR_SPD
134
135#define CONFIG_SYS_SPD_BUS_NUM 0
136#define SPD_EEPROM_ADDRESS 0x52
137#define CONFIG_SYS_SDRAM_SIZE 4096
138
139
140
141
142
143
144#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
145
146
147
148
149
150
151#define CONFIG_SYS_FLASH_BASE 0xe0000000
152#ifdef CONFIG_PHYS_64BIT
153#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
154#else
155#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
156#endif
157
158#define CONFIG_SYS_FLASH_BR_PRELIM \
159 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
160 BR_PS_16 | BR_V)
161#define CONFIG_SYS_FLASH_OR_PRELIM \
162 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
163 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
164
165#define CONFIG_FSL_CPLD
166#define CPLD_BASE 0xffdf0000
167#ifdef CONFIG_PHYS_64BIT
168#define CPLD_BASE_PHYS 0xfffdf0000ull
169#else
170#define CPLD_BASE_PHYS CPLD_BASE
171#endif
172
173#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
174#define CONFIG_SYS_OR3_PRELIM 0xffffeff7
175
176#define PIXIS_LBMAP_SWITCH 7
177#define PIXIS_LBMAP_MASK 0xf0
178#define PIXIS_LBMAP_SHIFT 4
179#define PIXIS_LBMAP_ALTBANK 0x40
180
181#define CONFIG_SYS_FLASH_QUIET_TEST
182#define CONFIG_FLASH_SHOW_PROGRESS 45
183
184#define CONFIG_SYS_MAX_FLASH_BANKS 1
185#define CONFIG_SYS_MAX_FLASH_SECT 1024
186#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
187#define CONFIG_SYS_FLASH_WRITE_TOUT 500
188
189#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
190
191#if defined(CONFIG_RAMBOOT_PBL)
192#define CONFIG_SYS_RAMBOOT
193#endif
194
195#define CONFIG_NAND_FSL_ELBC
196
197#ifdef CONFIG_NAND_FSL_ELBC
198#define CONFIG_SYS_NAND_BASE 0xffa00000
199#ifdef CONFIG_PHYS_64BIT
200#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
201#else
202#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
203#endif
204
205#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
206#define CONFIG_SYS_MAX_NAND_DEVICE 1
207#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
208
209
210#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
211 | (2<<BR_DECC_SHIFT) \
212 | BR_PS_8 \
213 | BR_MS_FCM \
214 | BR_V)
215#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 \
216 | OR_FCM_PGS \
217 | OR_FCM_CSCT \
218 | OR_FCM_CST \
219 | OR_FCM_CHT \
220 | OR_FCM_SCY_1 \
221 | OR_FCM_TRLX \
222 | OR_FCM_EHTR)
223
224#ifdef CONFIG_NAND
225#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
226#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
227#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM
228#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM
229#else
230#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM
231#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM
232#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
233#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
234#endif
235#else
236#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM
237#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM
238#endif
239
240#define CONFIG_SYS_FLASH_EMPTY_INFO
241#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
242#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
243
244#define CONFIG_HWCONFIG
245
246
247#define CONFIG_L1_INIT_RAM
248#define CONFIG_SYS_INIT_RAM_LOCK
249#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
250#ifdef CONFIG_PHYS_64BIT
251#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
252#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
253
254#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
255 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
256 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
257#else
258#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
259#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
260#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
261#endif
262#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
263
264#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
265 GENERATED_GBL_DATA_SIZE)
266#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
267
268#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
269#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
270
271
272
273
274
275#define CONFIG_SYS_NS16550_SERIAL
276#define CONFIG_SYS_NS16550_REG_SIZE 1
277#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
278
279#define CONFIG_SYS_BAUDRATE_TABLE \
280 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
281
282#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
283#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
284#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
285#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
286
287
288#define CONFIG_SYS_I2C
289#define CONFIG_SYS_I2C_FSL
290#define CONFIG_SYS_FSL_I2C_SPEED 400000
291#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
292#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
293#define CONFIG_SYS_FSL_I2C2_SPEED 400000
294#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
295#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
296
297
298
299
300#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
301#ifdef CONFIG_PHYS_64BIT
302#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
303#else
304#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
305#endif
306#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000
307
308#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
309#ifdef CONFIG_PHYS_64BIT
310#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
311#else
312#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
313#endif
314#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000
315
316
317
318
319
320#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
321#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
322#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000
323#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
324
325
326
327
328#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
329#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
330#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000
331
332
333#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
334#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001
335
336
337
338
339#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
340#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
341#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
342 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
343#endif
344
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353
354
355#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
356#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
357#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
358#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
359
360
361#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
362#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
363#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
364#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
365
366
367#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
368#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
369#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
370#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
371
372
373#define CONFIG_SYS_BMAN_NUM_PORTALS 10
374#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
375#ifdef CONFIG_PHYS_64BIT
376#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
377#else
378#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
379#endif
380#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
381#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
382#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
383#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
384#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
385#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
386 CONFIG_SYS_BMAN_CENA_SIZE)
387#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
388#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
389#define CONFIG_SYS_QMAN_NUM_PORTALS 10
390#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
391#ifdef CONFIG_PHYS_64BIT
392#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
393#else
394#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
395#endif
396#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
397#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
398#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
399#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
400#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
401#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
402 CONFIG_SYS_QMAN_CENA_SIZE)
403#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
404#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
405
406#define CONFIG_SYS_DPAA_FMAN
407#define CONFIG_SYS_DPAA_PME
408
409#if defined(CONFIG_SPIFLASH)
410
411
412
413
414#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
415#elif defined(CONFIG_SDCARD)
416
417
418
419
420
421#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
422#elif defined(CONFIG_NAND)
423#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
424#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
425
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427
428
429
430
431
432#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
433#else
434#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
435#endif
436#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
437#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
438
439#ifdef CONFIG_SYS_DPAA_FMAN
440#define CONFIG_PHYLIB_10G
441#define CONFIG_PHY_VITESSE
442#define CONFIG_PHY_TERANETICS
443#endif
444
445#ifdef CONFIG_PCI
446#if !defined(CONFIG_DM_PCI)
447#define CONFIG_FSL_PCI_INIT
448#define CONFIG_PCI_INDIRECT_BRIDGE
449#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
450#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
451#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
452#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
453#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
454#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000
455#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
456#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
457#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
458#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000
459#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
460#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
461#endif
462
463#define CONFIG_PCI_SCAN_SHOW
464#endif
465
466
467#define CONFIG_FSL_SATA_V2
468
469#ifdef CONFIG_FSL_SATA_V2
470#define CONFIG_SYS_SATA_MAX_DEVICE 2
471#define CONFIG_SATA1
472#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
473#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
474#define CONFIG_SATA2
475#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
476#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
477
478#define CONFIG_LBA48
479#endif
480
481#ifdef CONFIG_FMAN_ENET
482#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
483#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
484#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
485#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
486#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
487
488#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
489#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
490#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
491#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
492
493#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
494
495#define CONFIG_SYS_TBIPA_VALUE 8
496#define CONFIG_ETHPRIME "FM1@DTSEC1"
497#endif
498
499
500
501
502#define CONFIG_LOADS_ECHO
503#define CONFIG_SYS_LOADS_BAUD_CHANGE
504
505
506
507
508
509
510
511
512#define CONFIG_HAS_FSL_DR_USB
513#define CONFIG_HAS_FSL_MPH_USB
514
515#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
516#define CONFIG_USB_EHCI_FSL
517#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
518#endif
519
520#ifdef CONFIG_MMC
521#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
522#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
523#endif
524
525
526
527
528#define CONFIG_SYS_LOAD_ADDR 0x2000000
529
530
531
532
533
534
535#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
536#define CONFIG_SYS_BOOTM_LEN (64 << 20)
537
538#ifdef CONFIG_CMD_KGDB
539#define CONFIG_KGDB_BAUDRATE 230400
540#endif
541
542
543
544
545#define CONFIG_ROOTPATH "/opt/nfsroot"
546#define CONFIG_BOOTFILE "uImage"
547#define CONFIG_UBOOTPATH u-boot.bin
548
549
550#define CONFIG_LOADADDR 1000000
551
552#define __USB_PHY_TYPE utmi
553
554#define CONFIG_EXTRA_ENV_SETTINGS \
555 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
556 "bank_intlv=cs0_cs1\0" \
557 "netdev=eth0\0" \
558 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
559 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
560 "tftpflash=tftpboot $loadaddr $uboot && " \
561 "protect off $ubootaddr +$filesize && " \
562 "erase $ubootaddr +$filesize && " \
563 "cp.b $loadaddr $ubootaddr $filesize && " \
564 "protect on $ubootaddr +$filesize && " \
565 "cmp.b $loadaddr $ubootaddr $filesize\0" \
566 "consoledev=ttyS0\0" \
567 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
568 "usb_dr_mode=host\0" \
569 "ramdiskaddr=2000000\0" \
570 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \
571 "fdtaddr=1e00000\0" \
572 "fdtfile=p2041rdb/p2041rdb.dtb\0" \
573 "bdev=sda3\0"
574
575#define CONFIG_HDBOOT \
576 "setenv bootargs root=/dev/$bdev rw " \
577 "console=$consoledev,$baudrate $othbootargs;" \
578 "tftp $loadaddr $bootfile;" \
579 "tftp $fdtaddr $fdtfile;" \
580 "bootm $loadaddr - $fdtaddr"
581
582#define CONFIG_NFSBOOTCOMMAND \
583 "setenv bootargs root=/dev/nfs rw " \
584 "nfsroot=$serverip:$rootpath " \
585 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
586 "console=$consoledev,$baudrate $othbootargs;" \
587 "tftp $loadaddr $bootfile;" \
588 "tftp $fdtaddr $fdtfile;" \
589 "bootm $loadaddr - $fdtaddr"
590
591#define CONFIG_RAMBOOTCOMMAND \
592 "setenv bootargs root=/dev/ram rw " \
593 "console=$consoledev,$baudrate $othbootargs;" \
594 "tftp $ramdiskaddr $ramdiskfile;" \
595 "tftp $loadaddr $bootfile;" \
596 "tftp $fdtaddr $fdtfile;" \
597 "bootm $loadaddr $ramdiskaddr $fdtaddr"
598
599#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
600
601#include <asm/fsl_secure_boot.h>
602
603#endif
604