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10#ifndef __T1024QDS_H
11#define __T1024QDS_H
12
13
14#define CONFIG_SYS_BOOK3E_HV
15#define CONFIG_ENABLE_36BIT_PHYS
16
17#ifdef CONFIG_PHYS_64BIT
18#define CONFIG_ADDR_MAP 1
19#define CONFIG_SYS_NUM_ADDR_MAP 64
20#endif
21
22#define CONFIG_SYS_FSL_CPC
23#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
24
25#define CONFIG_ENV_OVERWRITE
26
27#define CONFIG_DEEP_SLEEP
28
29#ifdef CONFIG_RAMBOOT_PBL
30#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
31#define CONFIG_SPL_FLUSH_IMAGE
32#define CONFIG_SPL_PAD_TO 0x40000
33#define CONFIG_SPL_MAX_SIZE 0x28000
34#define RESET_VECTOR_OFFSET 0x27FFC
35#define BOOT_PAGE_OFFSET 0x27000
36#ifdef CONFIG_SPL_BUILD
37#define CONFIG_SPL_SKIP_RELOCATE
38#define CONFIG_SPL_COMMON_INIT_DDR
39#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
40#endif
41
42#ifdef CONFIG_NAND
43#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
44#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
45#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
46#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
47#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg
48#endif
49
50#ifdef CONFIG_SPIFLASH
51#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
52#define CONFIG_SPL_SPI_FLASH_MINIMAL
53#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
54#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
55#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
56#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
57#ifndef CONFIG_SPL_BUILD
58#define CONFIG_SYS_MPC85XX_NO_RESETVEC
59#endif
60#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg
61#endif
62
63#ifdef CONFIG_SDCARD
64#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
65#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
66#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
67#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
68#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
69#ifndef CONFIG_SPL_BUILD
70#define CONFIG_SYS_MPC85XX_NO_RESETVEC
71#endif
72#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg
73#endif
74
75#endif
76
77#ifndef CONFIG_RESET_VECTOR_ADDRESS
78#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
79#endif
80
81
82#define CONFIG_SRIO_PCIE_BOOT_MASTER
83
84
85
86
87#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
88#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000
89#ifdef CONFIG_PHYS_64BIT
90#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
91#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
92#else
93#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
94#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
95#endif
96
97
98
99
100#ifdef CONFIG_PHYS_64BIT
101#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
102#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
103#else
104#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
105#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
106#endif
107#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000
108
109#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
110#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001
111
112
113#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
114#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
115#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
116 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
117
118#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
119#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
120 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
121#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
122#endif
123
124#if defined(CONFIG_SPIFLASH)
125#define CONFIG_ENV_SIZE 0x2000
126#define CONFIG_ENV_OFFSET 0x100000
127#define CONFIG_ENV_SECT_SIZE 0x10000
128#elif defined(CONFIG_SDCARD)
129#define CONFIG_SYS_MMC_ENV_DEV 0
130#define CONFIG_ENV_SIZE 0x2000
131#define CONFIG_ENV_OFFSET (512 * 0x800)
132#elif defined(CONFIG_NAND)
133#define CONFIG_ENV_SIZE 0x2000
134#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
135#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
136#define CONFIG_ENV_ADDR 0xffe20000
137#define CONFIG_ENV_SIZE 0x2000
138#elif defined(CONFIG_ENV_IS_NOWHERE)
139#define CONFIG_ENV_SIZE 0x2000
140#else
141#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
142#define CONFIG_ENV_SIZE 0x2000
143#define CONFIG_ENV_SECT_SIZE 0x20000
144#endif
145
146#ifndef __ASSEMBLY__
147unsigned long get_board_sys_clk(void);
148unsigned long get_board_ddr_clk(void);
149#endif
150
151#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
152#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
153
154
155
156
157#define CONFIG_SYS_CACHE_STASHING
158#define CONFIG_BACKSIDE_L2_CACHE
159#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
160#define CONFIG_BTB
161#define CONFIG_DDR_ECC
162#ifdef CONFIG_DDR_ECC
163#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
164#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
165#endif
166
167#define CONFIG_SYS_MEMTEST_START 0x00200000
168#define CONFIG_SYS_MEMTEST_END 0x00400000
169
170
171
172
173#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
174#define CONFIG_SYS_L3_SIZE (256 << 10)
175#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
176#ifdef CONFIG_RAMBOOT_PBL
177#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
178#endif
179#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
180#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
181#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
182
183#ifdef CONFIG_PHYS_64BIT
184#define CONFIG_SYS_DCSRBAR 0xf0000000
185#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
186#endif
187
188
189#define CONFIG_ID_EEPROM
190#define CONFIG_SYS_I2C_EEPROM_NXID
191#define CONFIG_SYS_EEPROM_BUS_NUM 0
192#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
193#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
194#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
195#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
196
197
198
199
200#define CONFIG_VERY_BIG_RAM
201#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
202#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
203#define CONFIG_DIMM_SLOTS_PER_CTLR 1
204#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
205#define CONFIG_DDR_SPD
206
207#define CONFIG_SYS_SPD_BUS_NUM 0
208#define SPD_EEPROM_ADDRESS 0x51
209
210#define CONFIG_SYS_SDRAM_SIZE 4096
211
212
213
214
215#define CONFIG_SYS_FLASH_BASE 0xe0000000
216#ifdef CONFIG_PHYS_64BIT
217#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
218#else
219#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
220#endif
221
222#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
223#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
224 + 0x8000000) | \
225 CSPR_PORT_SIZE_16 | \
226 CSPR_MSEL_NOR | \
227 CSPR_V)
228#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
229#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
230 CSPR_PORT_SIZE_16 | \
231 CSPR_MSEL_NOR | \
232 CSPR_V)
233#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
234
235#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
236#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
237 FTIM0_NOR_TEADC(0x5) | \
238 FTIM0_NOR_TEAHC(0x5))
239#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
240 FTIM1_NOR_TRAD_NOR(0x1A) |\
241 FTIM1_NOR_TSEQRAD_NOR(0x13))
242#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
243 FTIM2_NOR_TCH(0x4) | \
244 FTIM2_NOR_TWPH(0x0E) | \
245 FTIM2_NOR_TWP(0x1c))
246#define CONFIG_SYS_NOR_FTIM3 0x0
247
248#define CONFIG_SYS_FLASH_QUIET_TEST
249#define CONFIG_FLASH_SHOW_PROGRESS 45
250
251#define CONFIG_SYS_MAX_FLASH_BANKS 2
252#define CONFIG_SYS_MAX_FLASH_SECT 1024
253#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
254#define CONFIG_SYS_FLASH_WRITE_TOUT 500
255
256#define CONFIG_SYS_FLASH_EMPTY_INFO
257#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
258 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
259#define CONFIG_FSL_QIXIS
260#define QIXIS_BASE 0xffdf0000
261#ifdef CONFIG_PHYS_64BIT
262#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
263#else
264#define QIXIS_BASE_PHYS QIXIS_BASE
265#endif
266#define QIXIS_LBMAP_SWITCH 0x06
267#define QIXIS_LBMAP_MASK 0x0f
268#define QIXIS_LBMAP_SHIFT 0
269#define QIXIS_LBMAP_DFLTBANK 0x00
270#define QIXIS_LBMAP_ALTBANK 0x04
271#define QIXIS_RST_CTL_RESET 0x31
272#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
273#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
274#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
275#define QIXIS_RST_FORCE_MEM 0x01
276
277#define CONFIG_SYS_CSPR3_EXT (0xf)
278#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
279 | CSPR_PORT_SIZE_8 \
280 | CSPR_MSEL_GPCM \
281 | CSPR_V)
282#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
283#define CONFIG_SYS_CSOR3 0x0
284
285#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
286 FTIM0_GPCM_TEADC(0x0e) | \
287 FTIM0_GPCM_TEAHC(0x0e))
288#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
289 FTIM1_GPCM_TRAD(0x3f))
290#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
291 FTIM2_GPCM_TCH(0x8) | \
292 FTIM2_GPCM_TWP(0x1f))
293#define CONFIG_SYS_CS3_FTIM3 0x0
294
295#define CONFIG_NAND_FSL_IFC
296#define CONFIG_SYS_NAND_BASE 0xff800000
297#ifdef CONFIG_PHYS_64BIT
298#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
299#else
300#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
301#endif
302#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
303#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
304 | CSPR_PORT_SIZE_8 \
305 | CSPR_MSEL_NAND \
306 | CSPR_V)
307#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
308
309#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
310 | CSOR_NAND_ECC_DEC_EN \
311 | CSOR_NAND_ECC_MODE_4 \
312 | CSOR_NAND_RAL_3 \
313 | CSOR_NAND_PGS_2K \
314 | CSOR_NAND_SPRZ_64 \
315 | CSOR_NAND_PB(64))
316
317#define CONFIG_SYS_NAND_ONFI_DETECTION
318
319
320#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
321 FTIM0_NAND_TWP(0x18) | \
322 FTIM0_NAND_TWCHT(0x07) | \
323 FTIM0_NAND_TWH(0x0a))
324#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
325 FTIM1_NAND_TWBE(0x39) | \
326 FTIM1_NAND_TRR(0x0e) | \
327 FTIM1_NAND_TRP(0x18))
328#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
329 FTIM2_NAND_TREH(0x0a) | \
330 FTIM2_NAND_TWHRE(0x1e))
331#define CONFIG_SYS_NAND_FTIM3 0x0
332
333#define CONFIG_SYS_NAND_DDR_LAW 11
334#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
335#define CONFIG_SYS_MAX_NAND_DEVICE 1
336
337#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
338
339#if defined(CONFIG_NAND)
340#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
341#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
342#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
343#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
344#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
345#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
346#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
347#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
348#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
349#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
350#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
351#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
352#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
353#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
354#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
355#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
356#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
357#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
358#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
359#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
360#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
361#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
362#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
363#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
364#else
365#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
366#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
367#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
368#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
369#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
370#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
371#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
372#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
373#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
374#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
375#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
376#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
377#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
378#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
379#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
380#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
381#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
382#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
383#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
384#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
385#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
386#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
387#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
388#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
389#endif
390
391#ifdef CONFIG_SPL_BUILD
392#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
393#else
394#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
395#endif
396
397#if defined(CONFIG_RAMBOOT_PBL)
398#define CONFIG_SYS_RAMBOOT
399#endif
400
401#define CONFIG_HWCONFIG
402
403
404#define CONFIG_L1_INIT_RAM
405#define CONFIG_SYS_INIT_RAM_LOCK
406#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000
407#ifdef CONFIG_PHYS_64BIT
408#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
409#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
410
411#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
412 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
413 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
414#else
415#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000
416#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
417#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
418#endif
419#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
420
421#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
422 GENERATED_GBL_DATA_SIZE)
423#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
424
425#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
426#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
427
428
429#define CONFIG_SYS_NS16550_SERIAL
430#define CONFIG_SYS_NS16550_REG_SIZE 1
431#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
432
433#define CONFIG_SYS_BAUDRATE_TABLE \
434 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
435
436#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
437#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
438#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
439#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
440
441
442#ifdef CONFIG_ARCH_T1024
443#define CONFIG_FSL_DIU_FB
444#ifdef CONFIG_FSL_DIU_FB
445#define CONFIG_FSL_DIU_CH7301
446#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
447#define CONFIG_VIDEO_LOGO
448#define CONFIG_VIDEO_BMP_LOGO
449#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
450
451
452
453
454#undef CONFIG_SYS_FLASH_EMPTY_INFO
455#endif
456#endif
457
458
459#define CONFIG_SYS_I2C
460#define CONFIG_SYS_I2C_FSL
461#define CONFIG_SYS_FSL_I2C_SPEED 50000
462#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
463#define CONFIG_SYS_FSL_I2C2_SPEED 50000
464#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
465#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
466#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
467
468#define I2C_MUX_PCA_ADDR 0x77
469#define I2C_MUX_PCA_ADDR_PRI 0x77
470#define I2C_MUX_PCA_ADDR_SEC 0x76
471#define I2C_RETIMER_ADDR 0x18
472
473
474#define I2C_MUX_CH_DEFAULT 0x8
475#define I2C_MUX_CH_DIU 0xC
476#define I2C_MUX_CH5 0xD
477#define I2C_MUX_CH7 0xF
478
479
480#define CONFIG_SYS_I2C_LDI_ADDR 0x38
481#define CONFIG_SYS_I2C_DVI_ADDR 0x75
482
483
484
485
486#define RTC
487#define CONFIG_RTC_DS3231 1
488#define CONFIG_SYS_I2C_RTC_ADDR 0x68
489
490
491
492
493
494
495
496
497
498#define CONFIG_PCIE1
499#define CONFIG_PCIE2
500#define CONFIG_PCIE3
501#define CONFIG_FSL_PCI_INIT
502#define CONFIG_SYS_PCI_64BIT
503#define CONFIG_PCI_INDIRECT_BRIDGE
504
505#ifdef CONFIG_PCI
506
507#ifdef CONFIG_PCIE1
508#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
509#ifdef CONFIG_PHYS_64BIT
510#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
511#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
512#else
513#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
514#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
515#endif
516#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
517#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
518#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
519#ifdef CONFIG_PHYS_64BIT
520#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
521#else
522#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
523#endif
524#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
525#endif
526
527
528#ifdef CONFIG_PCIE2
529#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
530#ifdef CONFIG_PHYS_64BIT
531#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
532#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
533#else
534#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
535#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
536#endif
537#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
538#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
539#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
540#ifdef CONFIG_PHYS_64BIT
541#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
542#else
543#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
544#endif
545#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
546#endif
547
548
549#ifdef CONFIG_PCIE3
550#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
551#ifdef CONFIG_PHYS_64BIT
552#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
553#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
554#else
555#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
556#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
557#endif
558#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000
559#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
560#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
561#ifdef CONFIG_PHYS_64BIT
562#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
563#else
564#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
565#endif
566#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
567#endif
568
569#define CONFIG_PCI_SCAN_SHOW
570#endif
571
572
573
574
575#define CONFIG_FSL_SATA_V2
576#ifdef CONFIG_FSL_SATA_V2
577#define CONFIG_SYS_SATA_MAX_DEVICE 1
578#define CONFIG_SATA1
579#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
580#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
581#define CONFIG_LBA48
582#endif
583
584
585
586
587#define CONFIG_HAS_FSL_DR_USB
588
589#ifdef CONFIG_HAS_FSL_DR_USB
590#define CONFIG_USB_EHCI_FSL
591#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
592#endif
593
594
595
596
597#ifdef CONFIG_MMC
598#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
599#endif
600
601
602#ifndef CONFIG_NOBQFMAN
603#define CONFIG_SYS_BMAN_NUM_PORTALS 10
604#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
605#ifdef CONFIG_PHYS_64BIT
606#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
607#else
608#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
609#endif
610#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
611#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
612#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
613#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
614#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
615#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
616 CONFIG_SYS_BMAN_CENA_SIZE)
617#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
618#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
619#define CONFIG_SYS_QMAN_NUM_PORTALS 10
620#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
621#ifdef CONFIG_PHYS_64BIT
622#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
623#else
624#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
625#endif
626#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
627#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
628#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
629#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
630#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
631#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
632 CONFIG_SYS_QMAN_CENA_SIZE)
633#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
634#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
635
636#define CONFIG_SYS_DPAA_FMAN
637
638
639#if defined(CONFIG_SPIFLASH)
640
641
642
643
644#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
645#define CONFIG_SYS_QE_FW_ADDR 0x130000
646#elif defined(CONFIG_SDCARD)
647
648
649
650
651
652#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
653#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
654#elif defined(CONFIG_NAND)
655#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
656#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
657#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
658
659
660
661
662
663
664
665#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
666#else
667#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
668#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
669#endif
670#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
671#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
672#endif
673
674#ifdef CONFIG_SYS_DPAA_FMAN
675#define CONFIG_PHYLIB_10G
676#define CONFIG_PHY_VITESSE
677#define CONFIG_PHY_REALTEK
678#define CONFIG_PHY_TERANETICS
679#define RGMII_PHY1_ADDR 0x1
680#define RGMII_PHY2_ADDR 0x2
681#define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
682#define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
683#define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
684#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
685#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
686#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
687#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
688#endif
689
690#ifdef CONFIG_FMAN_ENET
691#define CONFIG_ETHPRIME "FM1@DTSEC4"
692#endif
693
694
695
696
697
698
699
700
701#define CONFIG_LOADS_ECHO
702#define CONFIG_SYS_LOADS_BAUD_CHANGE
703
704
705
706
707#define CONFIG_SYS_LOAD_ADDR 0x2000000
708
709
710
711
712
713
714#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
715#define CONFIG_SYS_BOOTM_LEN (64 << 20)
716
717#ifdef CONFIG_CMD_KGDB
718#define CONFIG_KGDB_BAUDRATE 230400
719#endif
720
721
722
723
724#define CONFIG_ROOTPATH "/opt/nfsroot"
725#define CONFIG_BOOTFILE "uImage"
726#define CONFIG_UBOOTPATH "u-boot.bin"
727#define CONFIG_LOADADDR 1000000
728#define __USB_PHY_TYPE utmi
729
730#define CONFIG_EXTRA_ENV_SETTINGS \
731 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \
732 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
733 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
734 "ramdiskfile=t1024qds/ramdisk.uboot\0" \
735 "fdtfile=t1024qds/t1024qds.dtb\0" \
736 "netdev=eth0\0" \
737 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
738 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
739 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
740 "tftpflash=tftpboot $loadaddr $uboot && " \
741 "protect off $ubootaddr +$filesize && " \
742 "erase $ubootaddr +$filesize && " \
743 "cp.b $loadaddr $ubootaddr $filesize && " \
744 "protect on $ubootaddr +$filesize && " \
745 "cmp.b $loadaddr $ubootaddr $filesize\0" \
746 "consoledev=ttyS0\0" \
747 "ramdiskaddr=2000000\0" \
748 "fdtaddr=d00000\0" \
749 "bdev=sda3\0"
750
751#define CONFIG_LINUX \
752 "setenv bootargs root=/dev/ram rw " \
753 "console=$consoledev,$baudrate $othbootargs;" \
754 "setenv ramdiskaddr 0x02000000;" \
755 "setenv fdtaddr 0x00c00000;" \
756 "setenv loadaddr 0x1000000;" \
757 "bootm $loadaddr $ramdiskaddr $fdtaddr"
758
759#define CONFIG_NFSBOOTCOMMAND \
760 "setenv bootargs root=/dev/nfs rw " \
761 "nfsroot=$serverip:$rootpath " \
762 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
763 "console=$consoledev,$baudrate $othbootargs;" \
764 "tftp $loadaddr $bootfile;" \
765 "tftp $fdtaddr $fdtfile;" \
766 "bootm $loadaddr - $fdtaddr"
767
768#define CONFIG_BOOTCOMMAND CONFIG_LINUX
769
770#include <asm/fsl_secure_boot.h>
771
772#endif
773