LXR uboot/include/configs/T4240QDS.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
   4 */
   5
   6/*
   7 * T4240 QDS board configuration file
   8 */
   9#ifndef __CONFIG_H
  10#define __CONFIG_H
  11
  12#define CONFIG_FSL_SATA_V2
  13#define CONFIG_PCIE4
  14
  15#define CONFIG_ICS307_REFCLK_HZ         25000000  /* ICS307 ref clk freq */
  16
  17#ifdef CONFIG_RAMBOOT_PBL
  18#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg
  19#if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD)
  20#define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  21#define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  22#else
  23#define CONFIG_SPL_FLUSH_IMAGE
  24#define CONFIG_SPL_PAD_TO               0x40000
  25#define CONFIG_SPL_MAX_SIZE             0x28000
  26#define RESET_VECTOR_OFFSET             0x27FFC
  27#define BOOT_PAGE_OFFSET                0x27000
  28
  29#ifdef  CONFIG_NAND
  30#define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  31#define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  32#define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  33#define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  34#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_nand_rcw.cfg
  35#endif
  36
  37#ifdef  CONFIG_SDCARD
  38#define CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
  39#define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  40#define CONFIG_SYS_MMC_U_BOOT_DST       0x00200000
  41#define CONFIG_SYS_MMC_U_BOOT_START     0x00200000
  42#define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  43#ifndef CONFIG_SPL_BUILD
  44#define CONFIG_SYS_MPC85XX_NO_RESETVEC
  45#endif
  46#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_sd_rcw.cfg
  47#endif
  48
  49#ifdef CONFIG_SPL_BUILD
  50#define CONFIG_SPL_SKIP_RELOCATE
  51#define CONFIG_SPL_COMMON_INIT_DDR
  52#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  53#endif
  54
  55#endif
  56#endif /* CONFIG_RAMBOOT_PBL */
  57
  58#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  59/* Set 1M boot space */
  60#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  61#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  62                (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  63#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  64#endif
  65
  66#define CONFIG_SRIO_PCIE_BOOT_MASTER
  67#define CONFIG_DDR_ECC
  68
  69#include "t4qds.h"
  70
  71#if defined(CONFIG_SPIFLASH)
  72#define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  73#define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
  74#define CONFIG_ENV_SECT_SIZE            0x10000
  75#elif defined(CONFIG_SDCARD)
  76#define CONFIG_SYS_MMC_ENV_DEV          0
  77#define CONFIG_ENV_SIZE                 0x2000
  78#define CONFIG_ENV_OFFSET               (512 * 0x800)
  79#elif defined(CONFIG_NAND)
  80#define CONFIG_ENV_SIZE                 0x2000
  81#define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
  82#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  83#define CONFIG_ENV_ADDR         0xffe20000
  84#define CONFIG_ENV_SIZE         0x2000
  85#elif defined(CONFIG_ENV_IS_NOWHERE)
  86#define CONFIG_ENV_SIZE         0x2000
  87#else
  88#define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  89#define CONFIG_ENV_SIZE         0x2000
  90#define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
  91#endif
  92
  93#define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
  94#define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
  95
  96#ifndef __ASSEMBLY__
  97unsigned long get_board_sys_clk(void);
  98unsigned long get_board_ddr_clk(void);
  99#endif
 100
 101/* EEPROM */
 102#define CONFIG_ID_EEPROM
 103#define CONFIG_SYS_I2C_EEPROM_NXID
 104#define CONFIG_SYS_EEPROM_BUS_NUM       0
 105#define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 106#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 107
 108/*
 109 * DDR Setup
 110 */
 111#define CONFIG_SYS_SPD_BUS_NUM  0
 112#define SPD_EEPROM_ADDRESS1     0x51
 113#define SPD_EEPROM_ADDRESS2     0x52
 114#define SPD_EEPROM_ADDRESS3     0x53
 115#define SPD_EEPROM_ADDRESS4     0x54
 116#define SPD_EEPROM_ADDRESS5     0x55
 117#define SPD_EEPROM_ADDRESS6     0x56
 118#define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 119#define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 120
 121/*
 122 * IFC Definitions
 123 */
 124#define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 125#define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 126                                + 0x8000000) | \
 127                                CSPR_PORT_SIZE_16 | \
 128                                CSPR_MSEL_NOR | \
 129                                CSPR_V)
 130#define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 131#define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 132                                CSPR_PORT_SIZE_16 | \
 133                                CSPR_MSEL_NOR | \
 134                                CSPR_V)
 135#define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 136/* NOR Flash Timing Params */
 137#define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 138
 139#define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 140                                FTIM0_NOR_TEADC(0x5) | \
 141                                FTIM0_NOR_TEAHC(0x5))
 142#define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 143                                FTIM1_NOR_TRAD_NOR(0x1A) |\
 144                                FTIM1_NOR_TSEQRAD_NOR(0x13))
 145#define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 146                                FTIM2_NOR_TCH(0x4) | \
 147                                FTIM2_NOR_TWPH(0x0E) | \
 148                                FTIM2_NOR_TWP(0x1c))
 149#define CONFIG_SYS_NOR_FTIM3    0x0
 150
 151#define CONFIG_SYS_FLASH_QUIET_TEST
 152#define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 153
 154#define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 155#define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 156#define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 157#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 158
 159#define CONFIG_SYS_FLASH_EMPTY_INFO
 160#define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 161                                        + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 162
 163#define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 164#define QIXIS_BASE                      0xffdf0000
 165#define QIXIS_LBMAP_SWITCH              6
 166#define QIXIS_LBMAP_MASK                0x0f
 167#define QIXIS_LBMAP_SHIFT               0
 168#define QIXIS_LBMAP_DFLTBANK            0x00
 169#define QIXIS_LBMAP_ALTBANK             0x04
 170#define QIXIS_RST_CTL_RESET             0x83
 171#define QIXIS_RST_FORCE_MEM             0x1
 172#define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 173#define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 174#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 175#define QIXIS_BRDCFG5                   0x55
 176#define QIXIS_MUX_SDHC                  2
 177#define QIXIS_MUX_SDHC_WIDTH8           1
 178#define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 179
 180#define CONFIG_SYS_CSPR3_EXT    (0xf)
 181#define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 182                                | CSPR_PORT_SIZE_8 \
 183                                | CSPR_MSEL_GPCM \
 184                                | CSPR_V)
 185#define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 186#define CONFIG_SYS_CSOR3        0x0
 187/* QIXIS Timing parameters for IFC CS3 */
 188#define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 189                                        FTIM0_GPCM_TEADC(0x0e) | \
 190                                        FTIM0_GPCM_TEAHC(0x0e))
 191#define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 192                                        FTIM1_GPCM_TRAD(0x3f))
 193#define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 194                                        FTIM2_GPCM_TCH(0x8) | \
 195                                        FTIM2_GPCM_TWP(0x1f))
 196#define CONFIG_SYS_CS3_FTIM3            0x0
 197
 198/* NAND Flash on IFC */
 199#define CONFIG_NAND_FSL_IFC
 200#define CONFIG_SYS_NAND_BASE            0xff800000
 201#define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 202
 203#define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 204#define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 205                                | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 206                                | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 207                                | CSPR_V)
 208#define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 209
 210#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 211                                | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 212                                | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 213                                | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 214                                | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 215                                | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 216                                | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 217
 218#define CONFIG_SYS_NAND_ONFI_DETECTION
 219
 220/* ONFI NAND Flash mode0 Timing Params */
 221#define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 222                                        FTIM0_NAND_TWP(0x18)   | \
 223                                        FTIM0_NAND_TWCHT(0x07) | \
 224                                        FTIM0_NAND_TWH(0x0a))
 225#define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 226                                        FTIM1_NAND_TWBE(0x39)  | \
 227                                        FTIM1_NAND_TRR(0x0e)   | \
 228                                        FTIM1_NAND_TRP(0x18))
 229#define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 230                                        FTIM2_NAND_TREH(0x0a) | \
 231                                        FTIM2_NAND_TWHRE(0x1e))
 232#define CONFIG_SYS_NAND_FTIM3           0x0
 233
 234#define CONFIG_SYS_NAND_DDR_LAW         11
 235
 236#define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 237#define CONFIG_SYS_MAX_NAND_DEVICE      1
 238
 239#define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 240#define CONFIG_SYS_NAND_MAX_OOBFREE     2
 241#define CONFIG_SYS_NAND_MAX_ECCPOS      256
 242
 243#if defined(CONFIG_NAND)
 244#define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 245#define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 246#define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 247#define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 248#define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 249#define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 250#define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 251#define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 252#define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 253#define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 254#define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 255#define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 256#define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 257#define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 258#define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 259#define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 260#define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 261#define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 262#define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 263#define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 264#define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 265#define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 266#define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 267#define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 268#else
 269#define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 270#define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 271#define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 272#define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 273#define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 274#define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 275#define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 276#define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 277#define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 278#define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 279#define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 280#define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 281#define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 282#define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 283#define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 284#define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 285#define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 286#define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 287#define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 288#define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 289#define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 290#define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 291#define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 292#define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 293#endif
 294
 295#if defined(CONFIG_RAMBOOT_PBL)
 296#define CONFIG_SYS_RAMBOOT
 297#endif
 298
 299/* I2C */
 300#define CONFIG_SYS_FSL_I2C_SPEED        100000  /* I2C speed */
 301#define CONFIG_SYS_FSL_I2C2_SPEED       100000  /* I2C2 speed */
 302#define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
 303#define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
 304
 305#define I2C_MUX_CH_DEFAULT      0x8
 306#define I2C_MUX_CH_VOL_MONITOR  0xa
 307#define I2C_MUX_CH_VSC3316_FS   0xc
 308#define I2C_MUX_CH_VSC3316_BS   0xd
 309
 310/* Voltage monitor on channel 2*/
 311#define I2C_VOL_MONITOR_ADDR            0x40
 312#define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 313#define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 314#define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 315
 316/* VSC Crossbar switches */
 317#define CONFIG_VSC_CROSSBAR
 318#define VSC3316_FSM_TX_ADDR     0x70
 319#define VSC3316_FSM_RX_ADDR     0x71
 320
 321/*
 322 * RapidIO
 323 */
 324
 325/*
 326 * for slave u-boot IMAGE instored in master memory space,
 327 * PHYS must be aligned based on the SIZE
 328 */
 329#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 330#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 331#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 332#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 333/*
 334 * for slave UCODE and ENV instored in master memory space,
 335 * PHYS must be aligned based on the SIZE
 336 */
 337#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 338#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 339#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 340
 341/* slave core release by master*/
 342#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 343#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 344
 345/*
 346 * SRIO_PCIE_BOOT - SLAVE
 347 */
 348#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 349#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 350#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 351                (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 352#endif
 353/*
 354 * eSPI - Enhanced SPI
 355 */
 356
 357/* Qman/Bman */
 358#ifndef CONFIG_NOBQFMAN
 359#define CONFIG_SYS_BMAN_NUM_PORTALS     50
 360#define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 361#define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 362#define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 363#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 364#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 365#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 366#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 367#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 368                                        CONFIG_SYS_BMAN_CENA_SIZE)
 369#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 370#define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 371#define CONFIG_SYS_QMAN_NUM_PORTALS     50
 372#define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 373#define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 374#define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 375#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 376#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 377#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 378#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 379#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 380                                        CONFIG_SYS_QMAN_CENA_SIZE)
 381#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 382#define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 383
 384#define CONFIG_SYS_DPAA_FMAN
 385#define CONFIG_SYS_DPAA_PME
 386#define CONFIG_SYS_PMAN
 387#define CONFIG_SYS_DPAA_DCE
 388#define CONFIG_SYS_DPAA_RMAN
 389#define CONFIG_SYS_INTERLAKEN
 390
 391/* Default address of microcode for the Linux Fman driver */
 392#if defined(CONFIG_SPIFLASH)
 393/*
 394 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 395 * env, so we got 0x110000.
 396 */
 397#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 398#elif defined(CONFIG_SDCARD)
 399/*
 400 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 401 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 402 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 403 */
 404#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 405#elif defined(CONFIG_NAND)
 406#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 407#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 408/*
 409 * Slave has no ucode locally, it can fetch this from remote. When implementing
 410 * in two corenet boards, slave's ucode could be stored in master's memory
 411 * space, the address can be mapped from slave TLB->slave LAW->
 412 * slave SRIO or PCIE outbound window->master inbound window->
 413 * master LAW->the ucode address in master's memory space.
 414 */
 415#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 416#else
 417#define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 418#endif
 419#define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 420#define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 421#endif /* CONFIG_NOBQFMAN */
 422
 423#ifdef CONFIG_SYS_DPAA_FMAN
 424#define CONFIG_PHYLIB_10G
 425#define CONFIG_PHY_VITESSE
 426#define CONFIG_PHY_TERANETICS
 427#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 428#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 429#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 430#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 431#define FM1_10GEC1_PHY_ADDR     0x0
 432#define FM1_10GEC2_PHY_ADDR     0x1
 433#define FM2_10GEC1_PHY_ADDR     0x2
 434#define FM2_10GEC2_PHY_ADDR     0x3
 435#endif
 436
 437/* SATA */
 438#ifdef CONFIG_FSL_SATA_V2
 439#define CONFIG_SYS_SATA_MAX_DEVICE      2
 440#define CONFIG_SATA1
 441#define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 442#define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 443#define CONFIG_SATA2
 444#define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 445#define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 446
 447#define CONFIG_LBA48
 448#endif
 449
 450#ifdef CONFIG_FMAN_ENET
 451#define CONFIG_ETHPRIME         "FM1@DTSEC1"
 452#endif
 453
 454/*
 455* USB
 456*/
 457#define CONFIG_USB_EHCI_FSL
 458#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 459#define CONFIG_HAS_FSL_DR_USB
 460
 461#ifdef CONFIG_MMC
 462#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 463#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 464#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 465#define CONFIG_ESDHC_DETECT_QUIRK \
 466        (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
 467        IS_SVR_REV(get_svr(), 1, 0))
 468#define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \
 469        (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
 470#endif
 471
 472
 473#define __USB_PHY_TYPE  utmi
 474
 475/*
 476 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
 477 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
 478 * interleaving. It can be cacheline, page, bank, superbank.
 479 * See doc/README.fsl-ddr for details.
 480 */
 481#ifdef CONFIG_ARCH_T4240
 482#define CTRL_INTLV_PREFERED 3way_4KB
 483#else
 484#define CTRL_INTLV_PREFERED cacheline
 485#endif
 486
 487#define CONFIG_EXTRA_ENV_SETTINGS                               \
 488        "hwconfig=fsl_ddr:"                                     \
 489        "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 490        "bank_intlv=auto;"                                      \
 491        "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 492        "netdev=eth0\0"                                         \
 493        "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 494        "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
 495        "tftpflash=tftpboot $loadaddr $uboot && "               \
 496        "protect off $ubootaddr +$filesize && "                 \
 497        "erase $ubootaddr +$filesize && "                       \
 498        "cp.b $loadaddr $ubootaddr $filesize && "               \
 499        "protect on $ubootaddr +$filesize && "                  \
 500        "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 501        "consoledev=ttyS0\0"                                    \
 502        "ramdiskaddr=2000000\0"                                 \
 503        "ramdiskfile=t4240qds/ramdisk.uboot\0"                  \
 504        "fdtaddr=1e00000\0"                                     \
 505        "fdtfile=t4240qds/t4240qds.dtb\0"                               \
 506        "bdev=sda3\0"
 507
 508#define CONFIG_HVBOOT                           \
 509        "setenv bootargs config-addr=0x60000000; "      \
 510        "bootm 0x01000000 - 0x00f00000"
 511
 512#define CONFIG_ALU                              \
 513        "setenv bootargs root=/dev/$bdev rw "           \
 514        "console=$consoledev,$baudrate $othbootargs;"   \
 515        "cpu 1 release 0x01000000 - - -;"               \
 516        "cpu 2 release 0x01000000 - - -;"               \
 517        "cpu 3 release 0x01000000 - - -;"               \
 518        "cpu 4 release 0x01000000 - - -;"               \
 519        "cpu 5 release 0x01000000 - - -;"               \
 520        "cpu 6 release 0x01000000 - - -;"               \
 521        "cpu 7 release 0x01000000 - - -;"               \
 522        "go 0x01000000"
 523
 524#define CONFIG_LINUX                            \
 525        "setenv bootargs root=/dev/ram rw "             \
 526        "console=$consoledev,$baudrate $othbootargs;"   \
 527        "setenv ramdiskaddr 0x02000000;"                \
 528        "setenv fdtaddr 0x00c00000;"                    \
 529        "setenv loadaddr 0x1000000;"                    \
 530        "bootm $loadaddr $ramdiskaddr $fdtaddr"
 531
 532#define CONFIG_HDBOOT                                   \
 533        "setenv bootargs root=/dev/$bdev rw "           \
 534        "console=$consoledev,$baudrate $othbootargs;"   \
 535        "tftp $loadaddr $bootfile;"                     \
 536        "tftp $fdtaddr $fdtfile;"                       \
 537        "bootm $loadaddr - $fdtaddr"
 538
 539#define CONFIG_NFSBOOTCOMMAND                   \
 540        "setenv bootargs root=/dev/nfs rw "     \
 541        "nfsroot=$serverip:$rootpath "          \
 542        "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 543        "console=$consoledev,$baudrate $othbootargs;"   \
 544        "tftp $loadaddr $bootfile;"             \
 545        "tftp $fdtaddr $fdtfile;"               \
 546        "bootm $loadaddr - $fdtaddr"
 547
 548#define CONFIG_RAMBOOTCOMMAND                           \
 549        "setenv bootargs root=/dev/ram rw "             \
 550        "console=$consoledev,$baudrate $othbootargs;"   \
 551        "tftp $ramdiskaddr $ramdiskfile;"               \
 552        "tftp $loadaddr $bootfile;"                     \
 553        "tftp $fdtaddr $fdtfile;"                       \
 554        "bootm $loadaddr $ramdiskaddr $fdtaddr"
 555
 556#define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 557
 558#include <asm/fsl_secure_boot.h>
 559
 560#endif  /* __CONFIG_H */
 561