LXR uboot/include/configs/ethernut5.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * (C) Copyright 2011
   4 * egnite GmbH <info@egnite.de>
   5 *
   6 * Configuation settings for Ethernut 5 with AT91SAM9XE.
   7 */
   8
   9#ifndef __CONFIG_H
  10#define __CONFIG_H
  11
  12#include <asm/hardware.h>
  13
  14/* The first stage boot loader expects u-boot running at this address. */
  15
  16/* The first stage boot loader takes care of low level initialization. */
  17#define CONFIG_SKIP_LOWLEVEL_INIT
  18
  19/* Set our official architecture number. */
  20#define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5
  21
  22/* CPU information */
  23
  24/* ARM asynchronous clock */
  25#define CONFIG_SYS_AT91_SLOW_CLOCK      32768   /* slow clock xtal */
  26#define CONFIG_SYS_AT91_MAIN_CLOCK      18432000 /* 18.432 MHz crystal */
  27
  28/* 32kB internal SRAM */
  29#define CONFIG_SRAM_BASE        0x00300000 /*AT91SAM9XE_SRAM_BASE */
  30#define CONFIG_SRAM_SIZE        (32 << 10)
  31#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \
  32                                GENERATED_GBL_DATA_SIZE)
  33
  34/* 128MB SDRAM in 1 bank */
  35#define CONFIG_SYS_SDRAM_BASE           0x20000000
  36#define CONFIG_SYS_SDRAM_SIZE           (128 << 20)
  37#define CONFIG_SYS_LOAD_ADDR            CONFIG_SYS_SDRAM_BASE
  38#define CONFIG_LOADADDR                 CONFIG_SYS_LOAD_ADDR
  39#define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (1 << 20))
  40#define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE
  41#define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_TEXT_BASE \
  42                                        - CONFIG_SYS_MALLOC_LEN)
  43
  44/* 512kB on-chip NOR flash */
  45# define CONFIG_SYS_MAX_FLASH_BANKS     1
  46# define CONFIG_SYS_FLASH_BASE          0x00200000 /* AT91SAM9XE_FLASH_BASE */
  47# define CONFIG_AT91_EFLASH
  48# define CONFIG_SYS_MAX_FLASH_SECT      32
  49# define CONFIG_EFLASH_PROTSECTORS      1
  50
  51
  52/* bootstrap + u-boot + env + linux in dataflash on CS0 */
  53#define CONFIG_ENV_OFFSET       0x3DE000
  54
  55/* NAND flash */
  56#ifdef CONFIG_CMD_NAND
  57#define CONFIG_SYS_MAX_NAND_DEVICE      1
  58#define CONFIG_SYS_NAND_BASE            0x40000000
  59#define CONFIG_SYS_NAND_DBW_8
  60/* our ALE is AD21 */
  61#define CONFIG_SYS_NAND_MASK_ALE        (1 << 21)
  62/* our CLE is AD22 */
  63#define CONFIG_SYS_NAND_MASK_CLE        (1 << 22)
  64#define CONFIG_SYS_NAND_ENABLE_PIN      GPIO_PIN_PC(14)
  65#endif
  66
  67/* JFFS2 */
  68#ifdef CONFIG_CMD_JFFS2
  69#define CONFIG_JFFS2_CMDLINE
  70#define CONFIG_JFFS2_NAND
  71#endif
  72
  73/* Ethernet */
  74#define CONFIG_NET_RETRY_COUNT          20
  75#define CONFIG_MACB
  76#define CONFIG_RMII
  77#define CONFIG_PHY_ID                   0
  78#define CONFIG_MACB_SEARCH_PHY
  79
  80/* MMC */
  81#ifdef CONFIG_CMD_MMC
  82#define CONFIG_GENERIC_ATMEL_MCI
  83#define CONFIG_SYS_MMC_CD_PIN           AT91_PIO_PORTC, 8
  84#endif
  85
  86/* USB */
  87#ifdef CONFIG_CMD_USB
  88#define CONFIG_USB_ATMEL
  89#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
  90#define CONFIG_USB_OHCI_NEW
  91#define CONFIG_SYS_USB_OHCI_CPU_INIT
  92#define CONFIG_SYS_USB_OHCI_REGS_BASE   0x00500000
  93#define CONFIG_SYS_USB_OHCI_SLOT_NAME   "host"
  94#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
  95#endif
  96
  97/* RTC */
  98#if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
  99#define CONFIG_RTC_PCF8563
 100#define CONFIG_SYS_I2C_RTC_ADDR         0x51
 101#endif
 102
 103/* I2C */
 104#define CONFIG_SYS_MAX_I2C_BUS  1
 105
 106#define CONFIG_SYS_I2C
 107#define CONFIG_SYS_I2C_SOFT                     /* I2C bit-banged */
 108#define CONFIG_SYS_I2C_SOFT_SPEED       100000
 109#define CONFIG_SYS_I2C_SOFT_SLAVE       0
 110
 111#define I2C_SOFT_DECLARATIONS
 112
 113#define GPIO_I2C_SCL            AT91_PIO_PORTA, 24
 114#define GPIO_I2C_SDA            AT91_PIO_PORTA, 23
 115
 116#define I2C_INIT { \
 117        at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
 118        at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
 119        at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
 120        at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
 121        at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
 122}
 123
 124#define I2C_ACTIVE      at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
 125#define I2C_TRISTATE    at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
 126#define I2C_SCL(bit)    at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
 127#define I2C_SDA(bit)    at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
 128#define I2C_DELAY       udelay(100)
 129#define I2C_READ        at91_get_pio_value(AT91_PIO_PORTA, 23)
 130
 131/* DHCP/BOOTP options */
 132#ifdef CONFIG_CMD_DHCP
 133#define CONFIG_BOOTP_BOOTFILESIZE
 134#define CONFIG_SYS_AUTOLOAD     "n"
 135#endif
 136
 137/* File systems */
 138
 139/* Boot command */
 140#define CONFIG_CMDLINE_TAG
 141#define CONFIG_SETUP_MEMORY_TAGS
 142#define CONFIG_INITRD_TAG
 143#define CONFIG_BOOTCOMMAND      "sf probe 0:0; " \
 144                                "sf read 0x22000000 0xc6000 0x294000; " \
 145                                "bootm 0x22000000"
 146
 147/* Misc. u-boot settings */
 148
 149#endif
 150