1
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6
7#ifndef __LS2_RDB_H
8#define __LS2_RDB_H
9
10#include "ls2080a_common.h"
11
12#ifdef CONFIG_FSL_QSPI
13#ifdef CONFIG_TARGET_LS2081ARDB
14#define CONFIG_QIXIS_I2C_ACCESS
15#endif
16#ifndef CONFIG_DM_I2C
17#define CONFIG_SYS_I2C_EARLY_INIT
18#endif
19#endif
20
21#define I2C_MUX_CH_VOL_MONITOR 0xa
22#define I2C_VOL_MONITOR_ADDR 0x38
23#define CONFIG_VOL_MONITOR_IR36021_READ
24#define CONFIG_VOL_MONITOR_IR36021_SET
25
26#define CONFIG_VID_FLS_ENV "ls2080ardb_vdd_mv"
27#ifndef CONFIG_SPL_BUILD
28#define CONFIG_VID
29#endif
30
31#define IR_VDD_STEP_DOWN 5
32#define IR_VDD_STEP_UP 5
33
34#define VDD_MV_MIN 819
35#define VDD_MV_MAX 1212
36
37#ifndef __ASSEMBLY__
38unsigned long get_board_sys_clk(void);
39#endif
40
41#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
42#define CONFIG_DDR_CLK_FREQ 133333333
43#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
44
45#define CONFIG_DDR_SPD
46#define CONFIG_DDR_ECC
47#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
48#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
49#define SPD_EEPROM_ADDRESS1 0x51
50#define SPD_EEPROM_ADDRESS2 0x52
51#define SPD_EEPROM_ADDRESS3 0x53
52#define SPD_EEPROM_ADDRESS4 0x54
53#define SPD_EEPROM_ADDRESS5 0x55
54#define SPD_EEPROM_ADDRESS6 0x56
55#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
56#define CONFIG_SYS_SPD_BUS_NUM 0
57#define CONFIG_DIMM_SLOTS_PER_CTLR 2
58#define CONFIG_CHIP_SELECTS_PER_CTRL 4
59#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
60#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
61#endif
62
63
64#define CONFIG_SCSI_AHCI_PLAT
65
66#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
67#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
68
69#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
70#define CONFIG_SYS_SCSI_MAX_LUN 1
71#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
72 CONFIG_SYS_SCSI_MAX_LUN)
73#ifdef CONFIG_TFABOOT
74#define CONFIG_SYS_MMC_ENV_DEV 0
75
76#define CONFIG_ENV_SIZE 0x2000
77#define CONFIG_ENV_OFFSET 0x500000
78#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
79 CONFIG_ENV_OFFSET)
80#define CONFIG_ENV_SECT_SIZE 0x40000
81#endif
82
83#if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
84
85#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
86#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
87#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
88
89#define CONFIG_SYS_NOR0_CSPR \
90 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
91 CSPR_PORT_SIZE_16 | \
92 CSPR_MSEL_NOR | \
93 CSPR_V)
94#define CONFIG_SYS_NOR0_CSPR_EARLY \
95 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
96 CSPR_PORT_SIZE_16 | \
97 CSPR_MSEL_NOR | \
98 CSPR_V)
99#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
100#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
101 FTIM0_NOR_TEADC(0x5) | \
102 FTIM0_NOR_TEAHC(0x5))
103#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
104 FTIM1_NOR_TRAD_NOR(0x1a) |\
105 FTIM1_NOR_TSEQRAD_NOR(0x13))
106#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
107 FTIM2_NOR_TCH(0x4) | \
108 FTIM2_NOR_TWPH(0x0E) | \
109 FTIM2_NOR_TWP(0x1c))
110#define CONFIG_SYS_NOR_FTIM3 0x04000000
111#define CONFIG_SYS_IFC_CCR 0x01000000
112
113#ifdef CONFIG_MTD_NOR_FLASH
114#define CONFIG_SYS_FLASH_QUIET_TEST
115#define CONFIG_FLASH_SHOW_PROGRESS 45
116
117#define CONFIG_SYS_MAX_FLASH_BANKS 1
118#define CONFIG_SYS_MAX_FLASH_SECT 1024
119#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
120#define CONFIG_SYS_FLASH_WRITE_TOUT 500
121
122#define CONFIG_SYS_FLASH_EMPTY_INFO
123#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
124 CONFIG_SYS_FLASH_BASE + 0x40000000}
125#endif
126
127#define CONFIG_NAND_FSL_IFC
128#define CONFIG_SYS_NAND_MAX_ECCPOS 256
129#define CONFIG_SYS_NAND_MAX_OOBFREE 2
130
131#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
132#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
133 | CSPR_PORT_SIZE_8 \
134 | CSPR_MSEL_NAND \
135 | CSPR_V)
136#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
137
138#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
139 | CSOR_NAND_ECC_DEC_EN \
140 | CSOR_NAND_ECC_MODE_4 \
141 | CSOR_NAND_RAL_3 \
142 | CSOR_NAND_PGS_4K \
143 | CSOR_NAND_SPRZ_224 \
144 | CSOR_NAND_PB(128))
145
146#define CONFIG_SYS_NAND_ONFI_DETECTION
147
148
149#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \
150 FTIM0_NAND_TWP(0x30) | \
151 FTIM0_NAND_TWCHT(0x0e) | \
152 FTIM0_NAND_TWH(0x14))
153#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \
154 FTIM1_NAND_TWBE(0xab) | \
155 FTIM1_NAND_TRR(0x1c) | \
156 FTIM1_NAND_TRP(0x30))
157#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \
158 FTIM2_NAND_TREH(0x14) | \
159 FTIM2_NAND_TWHRE(0x3c))
160#define CONFIG_SYS_NAND_FTIM3 0x0
161
162#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
163#define CONFIG_SYS_MAX_NAND_DEVICE 1
164#define CONFIG_MTD_NAND_VERIFY_WRITE
165
166#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
167#define CONFIG_FSL_QIXIS
168#define QIXIS_LBMAP_SWITCH 0x06
169#define QIXIS_LBMAP_MASK 0x0f
170#define QIXIS_LBMAP_SHIFT 0
171#define QIXIS_LBMAP_DFLTBANK 0x00
172#define QIXIS_LBMAP_ALTBANK 0x04
173#define QIXIS_LBMAP_NAND 0x09
174#define QIXIS_RST_CTL_RESET 0x31
175#define QIXIS_RST_CTL_RESET_EN 0x30
176#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
177#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
178#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
179#define QIXIS_RCW_SRC_NAND 0x119
180#define QIXIS_RST_FORCE_MEM 0x01
181
182#define CONFIG_SYS_CSPR3_EXT (0x0)
183#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
184 | CSPR_PORT_SIZE_8 \
185 | CSPR_MSEL_GPCM \
186 | CSPR_V)
187#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
188 | CSPR_PORT_SIZE_8 \
189 | CSPR_MSEL_GPCM \
190 | CSPR_V)
191
192#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
193#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
194
195#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
196 FTIM0_GPCM_TEADC(0x0e) | \
197 FTIM0_GPCM_TEAHC(0x0e))
198#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
199 FTIM1_GPCM_TRAD(0x3f))
200#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
201 FTIM2_GPCM_TCH(0xf) | \
202 FTIM2_GPCM_TWP(0x3E))
203#define CONFIG_SYS_CS3_FTIM3 0x0
204
205#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
206#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
207#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY
208#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR
209#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
210#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
211#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
212#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
213#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
214#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
215#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
216#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
217#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
218#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
219#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
220#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
221#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
222#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
223
224#ifndef CONFIG_TFABOOT
225#define CONFIG_ENV_OFFSET (2048 * 1024)
226#define CONFIG_ENV_SECT_SIZE 0x20000
227#define CONFIG_ENV_SIZE 0x2000
228#endif
229#define CONFIG_SPL_PAD_TO 0x80000
230#define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024)
231#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
232#else
233#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
234#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
235#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
236#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
237#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
238#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
239#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
240#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
241#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
242#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
243#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
244#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
245#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
246#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
247#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
248#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
249#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
250
251#ifndef CONFIG_TFABOOT
252#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
253#define CONFIG_ENV_SECT_SIZE 0x20000
254#define CONFIG_ENV_SIZE 0x2000
255#endif
256#endif
257
258
259#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
260#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
261#endif
262#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
263
264#ifdef CONFIG_TARGET_LS2081ARDB
265#define CONFIG_FSL_QIXIS
266#define QIXIS_QMAP_MASK 0x07
267#define QIXIS_QMAP_SHIFT 5
268#define QIXIS_LBMAP_DFLTBANK 0x00
269#define QIXIS_LBMAP_QSPI 0x00
270#define QIXIS_RCW_SRC_QSPI 0x62
271#define QIXIS_LBMAP_ALTBANK 0x20
272#define QIXIS_RST_CTL_RESET 0x31
273#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
274#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
275#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
276#define QIXIS_LBMAP_MASK 0x0f
277#define QIXIS_RST_CTL_RESET_EN 0x30
278#endif
279
280
281
282
283#ifdef CONFIG_TARGET_LS2081ARDB
284#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
285#endif
286#define I2C_MUX_PCA_ADDR 0x75
287#define I2C_MUX_PCA_ADDR_PRI 0x75
288
289
290#define I2C_MUX_CH_DEFAULT 0x8
291
292
293#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
294#ifdef CONFIG_FSL_DSPI
295#define CONFIG_SPI_FLASH_STMICRO
296#endif
297#define FSL_QSPI_FLASH_SIZE SZ_64M
298#define FSL_QSPI_FLASH_NUM 2
299#endif
300
301
302
303
304#define RTC
305#ifdef CONFIG_TARGET_LS2081ARDB
306#define CONFIG_RTC_PCF8563 1
307#define CONFIG_SYS_I2C_RTC_ADDR 0x51
308#else
309#define CONFIG_RTC_DS3231 1
310#define CONFIG_SYS_I2C_RTC_ADDR 0x68
311#endif
312
313
314#define CONFIG_ID_EEPROM
315#define CONFIG_SYS_I2C_EEPROM_NXID
316#define CONFIG_SYS_EEPROM_BUS_NUM 0
317#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
318#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
319#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
320#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
321
322#define CONFIG_FSL_MEMAC
323
324#ifdef CONFIG_PCI
325#define CONFIG_PCI_SCAN_SHOW
326#endif
327
328
329#ifdef CONFIG_MMC
330#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
331#endif
332
333#define BOOT_TARGET_DEVICES(func) \
334 func(USB, usb, 0) \
335 func(MMC, mmc, 0) \
336 func(SCSI, scsi, 0) \
337 func(DHCP, dhcp, na)
338#include <config_distro_bootcmd.h>
339
340#ifdef CONFIG_TFABOOT
341#define QSPI_MC_INIT_CMD \
342 "env exists secureboot && " \
343 "esbc_validate 0x20700000 && " \
344 "esbc_validate 0x20740000;" \
345 "fsl_mc start mc 0x20a00000 0x20e00000 \0"
346#define SD_MC_INIT_CMD \
347 "mmcinfo;mmc read 0x80a00000 0x5000 0x1200;" \
348 "mmc read 0x80e00000 0x7000 0x800;" \
349 "env exists secureboot && " \
350 "mmc read 0x80700000 0x3800 0x10 && " \
351 "mmc read 0x80740000 0x3A00 0x10 && " \
352 "esbc_validate 0x80700000 && " \
353 "esbc_validate 0x80740000 ;" \
354 "fsl_mc start mc 0x80a00000 0x80e00000\0"
355#define IFC_MC_INIT_CMD \
356 "env exists secureboot && " \
357 "esbc_validate 0x580700000 && " \
358 "esbc_validate 0x580740000; " \
359 "fsl_mc start mc 0x580a00000 0x580e00000 \0"
360#else
361#ifdef CONFIG_QSPI_BOOT
362#define MC_INIT_CMD \
363 "mcinitcmd=env exists secureboot && " \
364 "esbc_validate 0x20700000 && " \
365 "esbc_validate 0x20740000;" \
366 "fsl_mc start mc 0x20a00000 0x20e00000 \0"
367#elif defined(CONFIG_SD_BOOT)
368#define MC_INIT_CMD \
369 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
370 "mmc read 0x80100000 0x7000 0x800;" \
371 "env exists secureboot && " \
372 "mmc read 0x80700000 0x3800 0x10 && " \
373 "mmc read 0x80740000 0x3A00 0x10 && " \
374 "esbc_validate 0x80700000 && " \
375 "esbc_validate 0x80740000 ;" \
376 "fsl_mc start mc 0x80000000 0x80100000\0" \
377 "mcmemsize=0x70000000\0"
378#else
379#define MC_INIT_CMD \
380 "mcinitcmd=env exists secureboot && " \
381 "esbc_validate 0x580700000 && " \
382 "esbc_validate 0x580740000; " \
383 "fsl_mc start mc 0x580a00000 0x580e00000 \0"
384#endif
385#endif
386
387
388#undef CONFIG_EXTRA_ENV_SETTINGS
389#ifdef CONFIG_TFABOOT
390#define CONFIG_EXTRA_ENV_SETTINGS \
391 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
392 "ramdisk_addr=0x800000\0" \
393 "ramdisk_size=0x2000000\0" \
394 "fdt_high=0xa0000000\0" \
395 "initrd_high=0xffffffffffffffff\0" \
396 "fdt_addr=0x64f00000\0" \
397 "kernel_addr=0x581000000\0" \
398 "kernel_start=0x1000000\0" \
399 "kernelheader_start=0x800000\0" \
400 "scriptaddr=0x80000000\0" \
401 "scripthdraddr=0x80080000\0" \
402 "fdtheader_addr_r=0x80100000\0" \
403 "kernelheader_addr_r=0x80200000\0" \
404 "kernelheader_addr=0x580800000\0" \
405 "kernel_addr_r=0x81000000\0" \
406 "kernelheader_size=0x40000\0" \
407 "fdt_addr_r=0x90000000\0" \
408 "load_addr=0xa0000000\0" \
409 "kernel_size=0x2800000\0" \
410 "kernel_addr_sd=0x8000\0" \
411 "kernel_size_sd=0x14000\0" \
412 "console=ttyAMA0,38400n8\0" \
413 "mcmemsize=0x70000000\0" \
414 "sd_bootcmd=echo Trying load from SD ..;" \
415 "mmcinfo; mmc read $load_addr " \
416 "$kernel_addr_sd $kernel_size_sd && " \
417 "bootm $load_addr#$board\0" \
418 QSPI_MC_INIT_CMD \
419 BOOTENV \
420 "boot_scripts=ls2088ardb_boot.scr\0" \
421 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
422 "scan_dev_for_boot_part=" \
423 "part list ${devtype} ${devnum} devplist; " \
424 "env exists devplist || setenv devplist 1; " \
425 "for distro_bootpart in ${devplist}; do " \
426 "if fstype ${devtype} " \
427 "${devnum}:${distro_bootpart} " \
428 "bootfstype; then " \
429 "run scan_dev_for_boot; " \
430 "fi; " \
431 "done\0" \
432 "boot_a_script=" \
433 "load ${devtype} ${devnum}:${distro_bootpart} " \
434 "${scriptaddr} ${prefix}${script}; " \
435 "env exists secureboot && load ${devtype} " \
436 "${devnum}:${distro_bootpart} " \
437 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
438 "&& esbc_validate ${scripthdraddr};" \
439 "source ${scriptaddr}\0" \
440 "qspi_bootcmd=echo Trying load from qspi..;" \
441 "sf probe && sf read $load_addr " \
442 "$kernel_start $kernel_size ; env exists secureboot &&" \
443 "sf read $kernelheader_addr_r $kernelheader_start " \
444 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
445 " bootm $load_addr#$board\0" \
446 "nor_bootcmd=echo Trying load from nor..;" \
447 "cp.b $kernel_addr $load_addr " \
448 "$kernel_size ; env exists secureboot && " \
449 "cp.b $kernelheader_addr $kernelheader_addr_r " \
450 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
451 "bootm $load_addr#$board\0"
452#else
453#define CONFIG_EXTRA_ENV_SETTINGS \
454 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
455 "ramdisk_addr=0x800000\0" \
456 "ramdisk_size=0x2000000\0" \
457 "fdt_high=0xa0000000\0" \
458 "initrd_high=0xffffffffffffffff\0" \
459 "fdt_addr=0x64f00000\0" \
460 "kernel_addr=0x581000000\0" \
461 "kernel_start=0x1000000\0" \
462 "kernelheader_start=0x800000\0" \
463 "scriptaddr=0x80000000\0" \
464 "scripthdraddr=0x80080000\0" \
465 "fdtheader_addr_r=0x80100000\0" \
466 "kernelheader_addr_r=0x80200000\0" \
467 "kernelheader_addr=0x580800000\0" \
468 "kernel_addr_r=0x81000000\0" \
469 "kernelheader_size=0x40000\0" \
470 "fdt_addr_r=0x90000000\0" \
471 "load_addr=0xa0000000\0" \
472 "kernel_size=0x2800000\0" \
473 "kernel_addr_sd=0x8000\0" \
474 "kernel_size_sd=0x14000\0" \
475 "console=ttyAMA0,38400n8\0" \
476 "mcmemsize=0x70000000\0" \
477 "sd_bootcmd=echo Trying load from SD ..;" \
478 "mmcinfo; mmc read $load_addr " \
479 "$kernel_addr_sd $kernel_size_sd && " \
480 "bootm $load_addr#$board\0" \
481 MC_INIT_CMD \
482 BOOTENV \
483 "boot_scripts=ls2088ardb_boot.scr\0" \
484 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
485 "scan_dev_for_boot_part=" \
486 "part list ${devtype} ${devnum} devplist; " \
487 "env exists devplist || setenv devplist 1; " \
488 "for distro_bootpart in ${devplist}; do " \
489 "if fstype ${devtype} " \
490 "${devnum}:${distro_bootpart} " \
491 "bootfstype; then " \
492 "run scan_dev_for_boot; " \
493 "fi; " \
494 "done\0" \
495 "boot_a_script=" \
496 "load ${devtype} ${devnum}:${distro_bootpart} " \
497 "${scriptaddr} ${prefix}${script}; " \
498 "env exists secureboot && load ${devtype} " \
499 "${devnum}:${distro_bootpart} " \
500 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
501 "env exists secureboot " \
502 "&& esbc_validate ${scripthdraddr};" \
503 "source ${scriptaddr}\0" \
504 "qspi_bootcmd=echo Trying load from qspi..;" \
505 "sf probe && sf read $load_addr " \
506 "$kernel_start $kernel_size ; env exists secureboot &&" \
507 "sf read $kernelheader_addr_r $kernelheader_start " \
508 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
509 " bootm $load_addr#$board\0" \
510 "nor_bootcmd=echo Trying load from nor..;" \
511 "cp.b $kernel_addr $load_addr " \
512 "$kernel_size ; env exists secureboot && " \
513 "cp.b $kernelheader_addr $kernelheader_addr_r " \
514 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
515 "bootm $load_addr#$board\0"
516#endif
517
518#ifdef CONFIG_TFABOOT
519#define QSPI_NOR_BOOTCOMMAND \
520 "env exists mcinitcmd && env exists secureboot "\
521 "&& esbc_validate 0x20780000; " \
522 "env exists mcinitcmd && " \
523 "fsl_mc lazyapply dpl 0x20d00000; " \
524 "run distro_bootcmd;run qspi_bootcmd; " \
525 "env exists secureboot && esbc_halt;"
526
527
528#define SD_BOOTCOMMAND \
529 "env exists mcinitcmd && env exists secureboot "\
530 "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \
531 "&& esbc_validate $load_addr; " \
532 "env exists mcinitcmd && run mcinitcmd " \
533 "&& mmc read 0x80d00000 0x6800 0x800 " \
534 "&& fsl_mc lazyapply dpl 0x80d00000; " \
535 "run distro_bootcmd;run sd_bootcmd; " \
536 "env exists secureboot && esbc_halt;"
537
538
539#define IFC_NOR_BOOTCOMMAND \
540 "env exists mcinitcmd && env exists secureboot "\
541 "&& esbc_validate 0x580780000; env exists mcinitcmd "\
542 "&& fsl_mc lazyapply dpl 0x580d00000;" \
543 "run distro_bootcmd;run nor_bootcmd; " \
544 "env exists secureboot && esbc_halt;"
545#else
546#undef CONFIG_BOOTCOMMAND
547#ifdef CONFIG_QSPI_BOOT
548
549#define CONFIG_BOOTCOMMAND \
550 "env exists mcinitcmd && env exists secureboot "\
551 "&& esbc_validate 0x20780000; " \
552 "env exists mcinitcmd && " \
553 "fsl_mc lazyapply dpl 0x20d00000; " \
554 "run distro_bootcmd;run qspi_bootcmd; " \
555 "env exists secureboot && esbc_halt;"
556#elif defined(CONFIG_SD_BOOT)
557
558#define CONFIG_BOOTCOMMAND \
559 "env exists mcinitcmd && env exists secureboot "\
560 "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \
561 "&& esbc_validate $load_addr; " \
562 "env exists mcinitcmd && run mcinitcmd " \
563 "&& mmc read 0x88000000 0x6800 0x800 " \
564 "&& fsl_mc lazyapply dpl 0x88000000; " \
565 "run distro_bootcmd;run sd_bootcmd; " \
566 "env exists secureboot && esbc_halt;"
567#else
568
569#define CONFIG_BOOTCOMMAND \
570 "env exists mcinitcmd && env exists secureboot "\
571 "&& esbc_validate 0x580780000; env exists mcinitcmd "\
572 "&& fsl_mc lazyapply dpl 0x580d00000;" \
573 "run distro_bootcmd;run nor_bootcmd; " \
574 "env exists secureboot && esbc_halt;"
575#endif
576#endif
577
578
579#ifdef CONFIG_FSL_MC_ENET
580#define CONFIG_PHY_CORTINA
581#define CONFIG_SYS_CORTINA_FW_IN_NOR
582#ifdef CONFIG_QSPI_BOOT
583#define CONFIG_CORTINA_FW_ADDR 0x20980000
584#else
585#define CONFIG_CORTINA_FW_ADDR 0x580980000
586#endif
587#define CONFIG_CORTINA_FW_LENGTH 0x40000
588
589#define CORTINA_PHY_ADDR1 0x10
590#define CORTINA_PHY_ADDR2 0x11
591#define CORTINA_PHY_ADDR3 0x12
592#define CORTINA_PHY_ADDR4 0x13
593#define AQ_PHY_ADDR1 0x00
594#define AQ_PHY_ADDR2 0x01
595#define AQ_PHY_ADDR3 0x02
596#define AQ_PHY_ADDR4 0x03
597#define AQR405_IRQ_MASK 0x36
598
599#define CONFIG_ETHPRIME "DPMAC1@xgmii"
600#endif
601
602#include <asm/fsl_secure_boot.h>
603
604#endif
605
