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10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13
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15
16
17
18
19
20#define CONFIG_MACH_OMAPL138_LCDK
21#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
22#define CONFIG_SYS_OSCIN_FREQ 24000000
23#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
24#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
25#define CONFIG_SYS_HZ 1000
26#define CONFIG_SKIP_LOWLEVEL_INIT
27
28
29
30
31#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024)
32#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE
33#define PHYS_SDRAM_1_SIZE (128 << 20)
34#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20)
35
36#define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
37#define CONFIG_SPL_BSS_MAX_SIZE 0x1080000
38
39
40#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
41
42
43#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
44
45#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
46 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
47 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
48 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
49 DAVINCI_SYSCFG_SUSPSRC_EMAC | \
50 DAVINCI_SYSCFG_SUSPSRC_I2C)
51
52
53
54
55
56
57#define CONFIG_SYS_DA850_PLL0_PLLM 18
58#define CONFIG_SYS_DA850_PLL1_PLLM 21
59
60
61
62
63#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
64 DV_DDR_PHY_EXT_STRBEN | \
65 (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
66
67#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
68 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
69 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
70 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
71 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
72 (4 << DV_DDR_SDCR_CL_SHIFT) | \
73 (3 << DV_DDR_SDCR_IBANK_SHIFT) | \
74 (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
75
76
77#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
78
79#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
80 (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \
81 (1 << DV_DDR_SDTMR1_RP_SHIFT) | \
82 (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
83 (2 << DV_DDR_SDTMR1_WR_SHIFT) | \
84 (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \
85 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
86 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
87 (1 << DV_DDR_SDTMR1_WTR_SHIFT))
88
89#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
90 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
91 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
92 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
93 (20 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
94 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
95 (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \
96 (2 << DV_DDR_SDTMR2_CKE_SHIFT))
97
98#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492
99#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
100
101
102
103
104#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
105
106#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
107#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
108
109
110
111
112#define CONFIG_SYS_DAVINCI_I2C_SPEED 25000
113#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10
114#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
115
116
117
118
119#ifdef CONFIG_NAND
120#define CONFIG_ENV_OFFSET 0x0
121#define CONFIG_ENV_SIZE (128 << 9)
122#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
123#define CONFIG_SYS_NAND_PAGE_2K
124#define CONFIG_SYS_NAND_CS 3
125#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
126#define CONFIG_SYS_NAND_MASK_CLE 0x10
127#define CONFIG_SYS_NAND_MASK_ALE 0x8
128#undef CONFIG_SYS_NAND_HW_ECC
129#define CONFIG_SYS_MAX_NAND_DEVICE 1
130#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
131#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
132#define CONFIG_SYS_NAND_5_ADDR_CYCLE
133#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
134#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
135#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
136#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
137#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
138#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
139 CONFIG_SYS_NAND_U_BOOT_SIZE - \
140 CONFIG_SYS_MALLOC_LEN - \
141 GENERATED_GBL_DATA_SIZE)
142#define CONFIG_SYS_NAND_ECCPOS { \
143 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
144 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
145 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
146 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
147#define CONFIG_SYS_NAND_PAGE_COUNT 64
148#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
149#define CONFIG_SYS_NAND_ECCSIZE 512
150#define CONFIG_SYS_NAND_ECCBYTES 10
151#define CONFIG_SYS_NAND_OOBSIZE 64
152#define CONFIG_SPL_NAND_BASE
153#define CONFIG_SPL_NAND_DRIVERS
154#define CONFIG_SPL_NAND_ECC
155#define CONFIG_SPL_NAND_LOAD
156#endif
157
158
159
160
161#ifdef CONFIG_DRIVER_TI_EMAC
162#undef CONFIG_DRIVER_TI_EMAC_USE_RMII
163#define CONFIG_BOOTP_DEFAULT
164#define CONFIG_BOOTP_DNS2
165#define CONFIG_BOOTP_SEND_HOSTNAME
166#define CONFIG_NET_RETRY_COUNT 10
167#endif
168
169
170
171
172#define CONFIG_BOOTFILE "zImage"
173#define CONFIG_SYS_CBSIZE 1024
174#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
175#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
176
177
178
179
180#define CONFIG_USB_OHCI_NEW
181#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
182
183
184
185
186#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
187#define CONFIG_CMDLINE_TAG
188#define CONFIG_REVISION_TAG
189#define CONFIG_SETUP_MEMORY_TAGS
190#define CONFIG_BOOTCOMMAND \
191 "run envboot; " \
192 "run mmcboot; "
193
194#define DEFAULT_LINUX_BOOT_ENV \
195 "loadaddr=0xc0700000\0" \
196 "fdtaddr=0xc0600000\0" \
197 "scriptaddr=0xc0600000\0"
198
199#include <environment/ti/mmc.h>
200
201#define CONFIG_EXTRA_ENV_SETTINGS \
202 DEFAULT_LINUX_BOOT_ENV \
203 DEFAULT_MMC_TI_ARGS \
204 "bootpart=0:2\0" \
205 "bootdir=/boot\0" \
206 "bootfile=zImage\0" \
207 "fdtfile=da850-lcdk.dtb\0" \
208 "boot_fdt=yes\0" \
209 "boot_fit=0\0" \
210 "console=ttyS2,115200n8\0"
211
212#ifdef CONFIG_CMD_BDI
213#define CONFIG_CLOCKS
214#endif
215
216
217
218#ifdef CONFIG_ENV_IS_IN_MMC
219#undef CONFIG_ENV_SIZE
220#undef CONFIG_ENV_OFFSET
221#define CONFIG_ENV_SIZE (16 << 10)
222#define CONFIG_ENV_OFFSET (51 << 9)
223#endif
224
225
226#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
227 CONFIG_SYS_MALLOC_LEN)
228#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
229#define CONFIG_SPL_STACK 0x8001ff00
230#define CONFIG_SPL_MAX_FOOTPRINT 32768
231#define CONFIG_SPL_PAD_TO 32768
232
233
234#define CONFIG_SYS_SDRAM_BASE 0xc0000000
235#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
236 GENERATED_GBL_DATA_SIZE)
237
238#include <asm/arch/hardware.h>
239
240#endif
241