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8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12#if defined(CONFIG_TARGET_P1020MBG)
13#define CONFIG_BOARDNAME "P1020MBG-PC"
14#define CONFIG_VSC7385_ENET
15#define CONFIG_SLIC
16#define __SW_BOOT_MASK 0x03
17#define __SW_BOOT_NOR 0xe4
18#define __SW_BOOT_SD 0x54
19#define CONFIG_SYS_L2_SIZE (256 << 10)
20#endif
21
22#if defined(CONFIG_TARGET_P1020UTM)
23#define CONFIG_BOARDNAME "P1020UTM-PC"
24#define __SW_BOOT_MASK 0x03
25#define __SW_BOOT_NOR 0xe0
26#define __SW_BOOT_SD 0x50
27#define CONFIG_SYS_L2_SIZE (256 << 10)
28#endif
29
30#if defined(CONFIG_TARGET_P1020RDB_PC)
31#define CONFIG_BOARDNAME "P1020RDB-PC"
32#define CONFIG_NAND_FSL_ELBC
33#define CONFIG_VSC7385_ENET
34#define CONFIG_SLIC
35#define __SW_BOOT_MASK 0x03
36#define __SW_BOOT_NOR 0x5c
37#define __SW_BOOT_SPI 0x1c
38#define __SW_BOOT_SD 0x9c
39#define __SW_BOOT_NAND 0xec
40#define __SW_BOOT_PCIE 0x6c
41#define CONFIG_SYS_L2_SIZE (256 << 10)
42#endif
43
44
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48
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51
52
53
54
55
56
57#if defined(CONFIG_TARGET_P1020RDB_PD)
58#define CONFIG_BOARDNAME "P1020RDB-PD"
59#define CONFIG_NAND_FSL_ELBC
60#define CONFIG_VSC7385_ENET
61#define CONFIG_SLIC
62#define __SW_BOOT_MASK 0x03
63#define __SW_BOOT_NOR 0x64
64#define __SW_BOOT_SPI 0x34
65#define __SW_BOOT_SD 0x24
66#define __SW_BOOT_NAND 0x44
67#define __SW_BOOT_PCIE 0x74
68#define CONFIG_SYS_L2_SIZE (256 << 10)
69
70
71
72#endif
73
74#if defined(CONFIG_TARGET_P1021RDB)
75#define CONFIG_BOARDNAME "P1021RDB-PC"
76#define CONFIG_NAND_FSL_ELBC
77#define CONFIG_VSC7385_ENET
78#define CONFIG_SYS_LBC_LBCR 0x00080000
79
80#define __SW_BOOT_MASK 0x03
81#define __SW_BOOT_NOR 0x5c
82#define __SW_BOOT_SPI 0x1c
83#define __SW_BOOT_SD 0x9c
84#define __SW_BOOT_NAND 0xec
85#define __SW_BOOT_PCIE 0x6c
86#define CONFIG_SYS_L2_SIZE (256 << 10)
87
88
89
90#endif
91
92#if defined(CONFIG_TARGET_P1024RDB)
93#define CONFIG_BOARDNAME "P1024RDB"
94#define CONFIG_NAND_FSL_ELBC
95#define CONFIG_SLIC
96#define __SW_BOOT_MASK 0xf3
97#define __SW_BOOT_NOR 0x00
98#define __SW_BOOT_SPI 0x08
99#define __SW_BOOT_SD 0x04
100#define __SW_BOOT_NAND 0x0c
101#define CONFIG_SYS_L2_SIZE (256 << 10)
102#endif
103
104#if defined(CONFIG_TARGET_P1025RDB)
105#define CONFIG_BOARDNAME "P1025RDB"
106#define CONFIG_NAND_FSL_ELBC
107#define CONFIG_SLIC
108
109#define CONFIG_SYS_LBC_LBCR 0x00080000
110
111#define __SW_BOOT_MASK 0xf3
112#define __SW_BOOT_NOR 0x00
113#define __SW_BOOT_SPI 0x08
114#define __SW_BOOT_SD 0x04
115#define __SW_BOOT_NAND 0x0c
116#define CONFIG_SYS_L2_SIZE (256 << 10)
117#endif
118
119#if defined(CONFIG_TARGET_P2020RDB)
120#define CONFIG_BOARDNAME "P2020RDB-PC"
121#define CONFIG_NAND_FSL_ELBC
122#define CONFIG_VSC7385_ENET
123#define __SW_BOOT_MASK 0x03
124#define __SW_BOOT_NOR 0xc8
125#define __SW_BOOT_SPI 0x28
126#define __SW_BOOT_SD 0x68
127#define __SW_BOOT_NAND 0xe8
128#define __SW_BOOT_PCIE 0xa8
129#define CONFIG_SYS_L2_SIZE (512 << 10)
130
131
132
133#endif
134
135#ifdef CONFIG_SDCARD
136#define CONFIG_SPL_FLUSH_IMAGE
137#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
138#define CONFIG_SPL_PAD_TO 0x20000
139#define CONFIG_SPL_MAX_SIZE (128 * 1024)
140#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
141#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
142#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
143#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
144#define CONFIG_SYS_MPC85XX_NO_RESETVEC
145#ifdef CONFIG_SPL_BUILD
146#define CONFIG_SPL_COMMON_INIT_DDR
147#endif
148#endif
149
150#ifdef CONFIG_SPIFLASH
151#define CONFIG_SPL_SPI_FLASH_MINIMAL
152#define CONFIG_SPL_FLUSH_IMAGE
153#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
154#define CONFIG_SPL_PAD_TO 0x20000
155#define CONFIG_SPL_MAX_SIZE (128 * 1024)
156#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
157#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
158#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
159#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
160#define CONFIG_SYS_MPC85XX_NO_RESETVEC
161#ifdef CONFIG_SPL_BUILD
162#define CONFIG_SPL_COMMON_INIT_DDR
163#endif
164#endif
165
166#ifdef CONFIG_NAND
167#ifdef CONFIG_TPL_BUILD
168#define CONFIG_SPL_FLUSH_IMAGE
169#define CONFIG_SPL_NAND_INIT
170#define CONFIG_SPL_COMMON_INIT_DDR
171#define CONFIG_SPL_MAX_SIZE (128 << 10)
172#define CONFIG_TPL_TEXT_BASE 0xf8f81000
173#define CONFIG_SYS_MPC85XX_NO_RESETVEC
174#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
175#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
176#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
177#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
178#elif defined(CONFIG_SPL_BUILD)
179#define CONFIG_SPL_INIT_MINIMAL
180#define CONFIG_SPL_FLUSH_IMAGE
181#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
182#define CONFIG_SPL_MAX_SIZE 4096
183#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
184#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
185#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
186#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
187#endif
188
189#define CONFIG_SPL_PAD_TO 0x20000
190#define CONFIG_TPL_PAD_TO 0x20000
191#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
192#endif
193
194#ifndef CONFIG_RESET_VECTOR_ADDRESS
195#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
196#endif
197
198#ifndef CONFIG_SYS_MONITOR_BASE
199#ifdef CONFIG_TPL_BUILD
200#define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
201#elif defined(CONFIG_SPL_BUILD)
202#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
203#else
204#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
205#endif
206#endif
207
208#define CONFIG_PCIE1
209#define CONFIG_PCIE2
210#define CONFIG_SYS_PCI_64BIT
211
212#define CONFIG_ENV_OVERWRITE
213
214#define CONFIG_SYS_SATA_MAX_DEVICE 2
215#define CONFIG_LBA48
216
217#if defined(CONFIG_TARGET_P2020RDB)
218#define CONFIG_SYS_CLK_FREQ 100000000
219#else
220#define CONFIG_SYS_CLK_FREQ 66666666
221#endif
222#define CONFIG_DDR_CLK_FREQ 66666666
223
224#define CONFIG_HWCONFIG
225
226
227
228#define CONFIG_L2_CACHE
229#define CONFIG_BTB
230
231#define CONFIG_ENABLE_36BIT_PHYS
232
233#ifdef CONFIG_PHYS_64BIT
234#define CONFIG_ADDR_MAP 1
235#define CONFIG_SYS_NUM_ADDR_MAP 16
236#endif
237
238#define CONFIG_SYS_MEMTEST_START 0x00200000
239#define CONFIG_SYS_MEMTEST_END 0x1fffffff
240
241#define CONFIG_SYS_CCSRBAR 0xffe00000
242#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
243
244
245
246#ifdef CONFIG_SPL_BUILD
247#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
248#endif
249
250
251#define CONFIG_SYS_DDR_RAW_TIMING
252#define CONFIG_DDR_SPD
253#define CONFIG_SYS_SPD_BUS_NUM 1
254#define SPD_EEPROM_ADDRESS 0x52
255
256#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
257#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
258#define CONFIG_CHIP_SELECTS_PER_CTRL 2
259#else
260#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
261#define CONFIG_CHIP_SELECTS_PER_CTRL 1
262#endif
263#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
264#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
265#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
266
267#define CONFIG_DIMM_SLOTS_PER_CTLR 1
268
269
270#ifndef CONFIG_TARGET_P2020RDB
271#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
272#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
273#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
274#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
275#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
276#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
277
278#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
279#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
280#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
281#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
282
283#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
284#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
285#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
286#define CONFIG_SYS_DDR_RCW_1 0x00000000
287#define CONFIG_SYS_DDR_RCW_2 0x00000000
288#define CONFIG_SYS_DDR_CONTROL 0xC70C0000
289#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
290#define CONFIG_SYS_DDR_TIMING_4 0x00220001
291#define CONFIG_SYS_DDR_TIMING_5 0x03402400
292
293#define CONFIG_SYS_DDR_TIMING_3 0x00020000
294#define CONFIG_SYS_DDR_TIMING_0 0x00330004
295#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
296#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
297#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
298#define CONFIG_SYS_DDR_MODE_1 0x40461520
299#define CONFIG_SYS_DDR_MODE_2 0x8000c000
300#define CONFIG_SYS_DDR_INTERVAL 0x0C300000
301#endif
302
303#undef CONFIG_CLOCKS_IN_MHZ
304
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324
325#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
326#define CONFIG_SYS_MAX_FLASH_SECT 512
327#define CONFIG_SYS_FLASH_BASE 0xec000000
328#elif defined(CONFIG_TARGET_P1020UTM)
329#define CONFIG_SYS_MAX_FLASH_SECT 256
330#define CONFIG_SYS_FLASH_BASE 0xee000000
331#else
332#define CONFIG_SYS_MAX_FLASH_SECT 128
333#define CONFIG_SYS_FLASH_BASE 0xef000000
334#endif
335
336#ifdef CONFIG_PHYS_64BIT
337#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
338#else
339#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
340#endif
341
342#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
343 | BR_PS_16 | BR_V)
344
345#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
346
347#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
348#define CONFIG_SYS_FLASH_QUIET_TEST
349#define CONFIG_FLASH_SHOW_PROGRESS 45
350
351#define CONFIG_SYS_MAX_FLASH_BANKS 1
352
353#undef CONFIG_SYS_FLASH_CHECKSUM
354#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
355#define CONFIG_SYS_FLASH_WRITE_TOUT 500
356
357#define CONFIG_SYS_FLASH_EMPTY_INFO
358
359
360#ifdef CONFIG_NAND_FSL_ELBC
361#define CONFIG_SYS_NAND_BASE 0xff800000
362#ifdef CONFIG_PHYS_64BIT
363#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
364#else
365#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
366#endif
367
368#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
369#define CONFIG_SYS_MAX_NAND_DEVICE 1
370#if defined(CONFIG_TARGET_P1020RDB_PD)
371#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
372#else
373#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
374#endif
375
376#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
377 | (2<<BR_DECC_SHIFT) \
378 | BR_PS_8 \
379 | BR_MS_FCM \
380 | BR_V)
381#if defined(CONFIG_TARGET_P1020RDB_PD)
382#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
383 | OR_FCM_PGS \
384 | OR_FCM_CSCT \
385 | OR_FCM_CST \
386 | OR_FCM_CHT \
387 | OR_FCM_SCY_1 \
388 | OR_FCM_TRLX \
389 | OR_FCM_EHTR)
390#else
391#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
392 | OR_FCM_CSCT \
393 | OR_FCM_CST \
394 | OR_FCM_CHT \
395 | OR_FCM_SCY_1 \
396 | OR_FCM_TRLX \
397 | OR_FCM_EHTR)
398#endif
399#endif
400
401#define CONFIG_SYS_INIT_RAM_LOCK
402#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
403#ifdef CONFIG_PHYS_64BIT
404#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
405#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
406
407#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
408 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
409 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
410#else
411
412#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
413#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
414#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
415#endif
416
417#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
418
419#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
420 GENERATED_GBL_DATA_SIZE)
421#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
422
423#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
424#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
425
426#define CONFIG_SYS_CPLD_BASE 0xffa00000
427#ifdef CONFIG_PHYS_64BIT
428#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
429#else
430#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
431#endif
432
433#define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
434 BR_PS_8 | BR_V)
435#define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
436
437#define CONFIG_SYS_PMC_BASE 0xff980000
438#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
439#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
440 BR_PS_8 | BR_V)
441#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
442 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
443 OR_GPCM_EAD)
444
445#ifdef CONFIG_NAND
446#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
447#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
448#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM
449#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM
450#else
451#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM
452#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM
453#ifdef CONFIG_NAND_FSL_ELBC
454#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
455#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
456#endif
457#endif
458#define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM
459#define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM
460
461
462#ifdef CONFIG_VSC7385_ENET
463#define CONFIG_SYS_VSC7385_BASE 0xffb00000
464
465#ifdef CONFIG_PHYS_64BIT
466#define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
467#else
468#define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
469#endif
470
471#define CONFIG_SYS_VSC7385_BR_PRELIM \
472 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
473#define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
474 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
475 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
476
477#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
478#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
479
480
481#define CONFIG_VSC7385_IMAGE_SIZE 8192
482#endif
483
484
485
486
487#if defined(CONFIG_SPL_BUILD)
488#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
489#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
490#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
491#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
492#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
493#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
494#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
495#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
496#if defined(CONFIG_TARGET_P2020RDB)
497#define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
498#else
499#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
500#endif
501#elif defined(CONFIG_NAND)
502#ifdef CONFIG_TPL_BUILD
503#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
504#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
505#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
506#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
507#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
508#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
509#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
510#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
511#else
512#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
513#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
514#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
515#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
516#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
517#endif
518#endif
519#endif
520
521
522
523
524
525#undef CONFIG_SERIAL_SOFTWARE_FIFO
526#define CONFIG_SYS_NS16550_SERIAL
527#define CONFIG_SYS_NS16550_REG_SIZE 1
528#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
529#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
530#define CONFIG_NS16550_MIN_FUNCTIONS
531#endif
532
533#define CONFIG_SYS_BAUDRATE_TABLE \
534 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
535
536#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
537#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
538
539
540#define CONFIG_SYS_I2C
541#define CONFIG_SYS_I2C_FSL
542#define CONFIG_SYS_FSL_I2C_SPEED 400000
543#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
544#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
545#define CONFIG_SYS_FSL_I2C2_SPEED 400000
546#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
547#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
548#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
549#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
550#define CONFIG_SYS_SPD_BUS_NUM 1
551
552
553
554
555#undef CONFIG_ID_EEPROM
556
557#define CONFIG_RTC_PT7C4338
558#define CONFIG_SYS_I2C_RTC_ADDR 0x68
559#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
560
561
562#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
563#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
564#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
565
566#if defined(CONFIG_PCI)
567
568
569
570
571
572
573#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
574#ifdef CONFIG_PHYS_64BIT
575#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
576#else
577#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
578#endif
579#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
580#ifdef CONFIG_PHYS_64BIT
581#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
582#else
583#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
584#endif
585
586
587#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
588#ifdef CONFIG_PHYS_64BIT
589#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
590#else
591#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
592#endif
593#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
594#ifdef CONFIG_PHYS_64BIT
595#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
596#else
597#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
598#endif
599
600#if !defined(CONFIG_DM_PCI)
601#define CONFIG_FSL_PCI_INIT
602#define CONFIG_PCI_INDIRECT_BRIDGE
603#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
604#ifdef CONFIG_PHYS_64BIT
605#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
606#else
607#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
608#endif
609#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000
610#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
611#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
612
613#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
614#ifdef CONFIG_PHYS_64BIT
615#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
616#else
617#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
618#endif
619#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
620#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
621#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
622#endif
623
624#define CONFIG_PCI_SCAN_SHOW
625#endif
626
627#if defined(CONFIG_TSEC_ENET)
628#define CONFIG_TSEC1
629#define CONFIG_TSEC1_NAME "eTSEC1"
630#define CONFIG_TSEC2
631#define CONFIG_TSEC2_NAME "eTSEC2"
632#define CONFIG_TSEC3
633#define CONFIG_TSEC3_NAME "eTSEC3"
634
635#define TSEC1_PHY_ADDR 2
636#define TSEC2_PHY_ADDR 0
637#define TSEC3_PHY_ADDR 1
638
639#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
640#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
641#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
642
643#define TSEC1_PHYIDX 0
644#define TSEC2_PHYIDX 0
645#define TSEC3_PHYIDX 0
646
647#define CONFIG_ETHPRIME "eTSEC1"
648
649#define CONFIG_HAS_ETH0
650#define CONFIG_HAS_ETH1
651#define CONFIG_HAS_ETH2
652#endif
653
654#ifdef CONFIG_QE
655
656#define CONFIG_SYS_QE_FW_ADDR 0xefec0000
657#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
658#endif
659
660#ifdef CONFIG_TARGET_P1025RDB
661
662
663
664#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
665
666#undef CONFIG_UEC_ETH
667#define CONFIG_PHY_MODE_NEED_CHANGE
668
669#define CONFIG_UEC_ETH1
670#define CONFIG_HAS_ETH0
671
672#ifdef CONFIG_UEC_ETH1
673#define CONFIG_SYS_UEC1_UCC_NUM 0
674#define CONFIG_SYS_UEC1_RX_CLK QE_CLK12
675#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9
676#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
677#define CONFIG_SYS_UEC1_PHY_ADDR 0x0
678#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
679#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
680#endif
681
682#define CONFIG_UEC_ETH5
683#define CONFIG_HAS_ETH1
684
685#ifdef CONFIG_UEC_ETH5
686#define CONFIG_SYS_UEC5_UCC_NUM 4
687#define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
688#define CONFIG_SYS_UEC5_TX_CLK QE_CLK13
689#define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
690#define CONFIG_SYS_UEC5_PHY_ADDR 0x3
691#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
692#define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
693#endif
694#endif
695
696
697
698
699#ifdef CONFIG_SPIFLASH
700#define CONFIG_ENV_SIZE 0x2000
701#define CONFIG_ENV_OFFSET 0x100000
702#define CONFIG_ENV_SECT_SIZE 0x10000
703#elif defined(CONFIG_SDCARD)
704#define CONFIG_FSL_FIXED_MMC_LOCATION
705#define CONFIG_ENV_SIZE 0x2000
706#define CONFIG_SYS_MMC_ENV_DEV 0
707#elif defined(CONFIG_NAND)
708#ifdef CONFIG_TPL_BUILD
709#define CONFIG_ENV_SIZE 0x2000
710#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
711#else
712#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
713#endif
714#define CONFIG_ENV_OFFSET (1024 * 1024)
715#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
716#elif defined(CONFIG_SYS_RAMBOOT)
717#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
718#define CONFIG_ENV_SIZE 0x2000
719#else
720#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
721#define CONFIG_ENV_SIZE 0x2000
722#define CONFIG_ENV_SECT_SIZE 0x20000
723#endif
724
725#define CONFIG_LOADS_ECHO
726#define CONFIG_SYS_LOADS_BAUD_CHANGE
727
728
729
730
731#define CONFIG_HAS_FSL_DR_USB
732
733#if defined(CONFIG_HAS_FSL_DR_USB)
734#ifdef CONFIG_USB_EHCI_HCD
735#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
736#define CONFIG_USB_EHCI_FSL
737#endif
738#endif
739
740#if defined(CONFIG_TARGET_P1020RDB_PD)
741#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
742#endif
743
744#ifdef CONFIG_MMC
745#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
746#endif
747
748#undef CONFIG_WATCHDOG
749
750
751
752
753#define CONFIG_SYS_LOAD_ADDR 0x2000000
754
755
756
757
758
759
760#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
761#define CONFIG_SYS_BOOTM_LEN (64 << 20)
762
763#if defined(CONFIG_CMD_KGDB)
764#define CONFIG_KGDB_BAUDRATE 230400
765#endif
766
767
768
769
770#define CONFIG_HOSTNAME "unknown"
771#define CONFIG_ROOTPATH "/opt/nfsroot"
772#define CONFIG_BOOTFILE "uImage"
773#define CONFIG_UBOOTPATH u-boot.bin
774
775
776#define CONFIG_LOADADDR 1000000
777
778#ifdef __SW_BOOT_NOR
779#define __NOR_RST_CMD \
780norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
781i2c mw 18 3 __SW_BOOT_MASK 1; reset
782#endif
783#ifdef __SW_BOOT_SPI
784#define __SPI_RST_CMD \
785spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
786i2c mw 18 3 __SW_BOOT_MASK 1; reset
787#endif
788#ifdef __SW_BOOT_SD
789#define __SD_RST_CMD \
790sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
791i2c mw 18 3 __SW_BOOT_MASK 1; reset
792#endif
793#ifdef __SW_BOOT_NAND
794#define __NAND_RST_CMD \
795nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
796i2c mw 18 3 __SW_BOOT_MASK 1; reset
797#endif
798#ifdef __SW_BOOT_PCIE
799#define __PCIE_RST_CMD \
800pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
801i2c mw 18 3 __SW_BOOT_MASK 1; reset
802#endif
803
804#define CONFIG_EXTRA_ENV_SETTINGS \
805"netdev=eth0\0" \
806"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
807"loadaddr=1000000\0" \
808"bootfile=uImage\0" \
809"tftpflash=tftpboot $loadaddr $uboot; " \
810 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
811 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
812 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
813 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
814 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
815"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
816"consoledev=ttyS0\0" \
817"ramdiskaddr=2000000\0" \
818"ramdiskfile=rootfs.ext2.gz.uboot\0" \
819"fdtaddr=1e00000\0" \
820"bdev=sda1\0" \
821"jffs2nor=mtdblock3\0" \
822"norbootaddr=ef080000\0" \
823"norfdtaddr=ef040000\0" \
824"jffs2nand=mtdblock9\0" \
825"nandbootaddr=100000\0" \
826"nandfdtaddr=80000\0" \
827"ramdisk_size=120000\0" \
828"map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
829"map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
830__stringify(__NOR_RST_CMD)"\0" \
831__stringify(__SPI_RST_CMD)"\0" \
832__stringify(__SD_RST_CMD)"\0" \
833__stringify(__NAND_RST_CMD)"\0" \
834__stringify(__PCIE_RST_CMD)"\0"
835
836#define CONFIG_NFSBOOTCOMMAND \
837"setenv bootargs root=/dev/nfs rw " \
838"nfsroot=$serverip:$rootpath " \
839"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
840"console=$consoledev,$baudrate $othbootargs;" \
841"tftp $loadaddr $bootfile;" \
842"tftp $fdtaddr $fdtfile;" \
843"bootm $loadaddr - $fdtaddr"
844
845#define CONFIG_HDBOOT \
846"setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
847"console=$consoledev,$baudrate $othbootargs;" \
848"usb start;" \
849"ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
850"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
851"bootm $loadaddr - $fdtaddr"
852
853#define CONFIG_USB_FAT_BOOT \
854"setenv bootargs root=/dev/ram rw " \
855"console=$consoledev,$baudrate $othbootargs " \
856"ramdisk_size=$ramdisk_size;" \
857"usb start;" \
858"fatload usb 0:2 $loadaddr $bootfile;" \
859"fatload usb 0:2 $fdtaddr $fdtfile;" \
860"fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
861"bootm $loadaddr $ramdiskaddr $fdtaddr"
862
863#define CONFIG_USB_EXT2_BOOT \
864"setenv bootargs root=/dev/ram rw " \
865"console=$consoledev,$baudrate $othbootargs " \
866"ramdisk_size=$ramdisk_size;" \
867"usb start;" \
868"ext2load usb 0:4 $loadaddr $bootfile;" \
869"ext2load usb 0:4 $fdtaddr $fdtfile;" \
870"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
871"bootm $loadaddr $ramdiskaddr $fdtaddr"
872
873#define CONFIG_NORBOOT \
874"setenv bootargs root=/dev/$jffs2nor rw " \
875"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
876"bootm $norbootaddr - $norfdtaddr"
877
878#define CONFIG_RAMBOOTCOMMAND \
879"setenv bootargs root=/dev/ram rw " \
880"console=$consoledev,$baudrate $othbootargs " \
881"ramdisk_size=$ramdisk_size;" \
882"tftp $ramdiskaddr $ramdiskfile;" \
883"tftp $loadaddr $bootfile;" \
884"tftp $fdtaddr $fdtfile;" \
885"bootm $loadaddr $ramdiskaddr $fdtaddr"
886
887#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
888
889#endif
890