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19#ifndef __CONFIG_H
20#define __CONFIG_H
21
22
23#define CONFIG_LINUX_RESET_VEC 0x100
24
25#ifdef RUN_DIAG
26#define CONFIG_SYS_DIAG_ADDR 0xff800000
27#endif
28
29#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
30
31
32
33
34
35#define CONFIG_SYS_SCRATCH_VA 0xe8000000
36
37#define CONFIG_SYS_SRIO
38#define CONFIG_SRIO1
39
40#define CONFIG_PCIE1 1
41#define CONFIG_PCIE2 1
42#define CONFIG_FSL_PCI_INIT 1
43#define CONFIG_PCI_INDIRECT_BRIDGE 1
44
45#define CONFIG_ENV_OVERWRITE
46
47#define CONFIG_BAT_RW 1
48
49#undef CONFIG_SPD_EEPROM
50#undef CONFIG_DDR_ECC
51#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
52#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
53#define CACHE_LINE_INTERLEAVING 0x20000000
54#define PAGE_INTERLEAVING 0x21000000
55#define BANK_INTERLEAVING 0x22000000
56#define SUPER_BANK_INTERLEAVING 0x23000000
57
58#define CONFIG_ALTIVEC 1
59
60
61
62
63#define CONFIG_SYS_L2
64#define L2_INIT 0
65#define L2_ENABLE (L2CR_L2E)
66
67#ifndef CONFIG_SYS_CLK_FREQ
68#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
69#endif
70
71#undef CONFIG_SYS_DRAM_TEST
72#define CONFIG_SYS_MEMTEST_START 0x00200000
73#define CONFIG_SYS_MEMTEST_END 0x00400000
74
75
76
77
78
79#define CONFIG_SYS_CCSRBAR 0xf8000000
80#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
81
82#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
83#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
84#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
85
86
87
88
89#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
90#define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000
91#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
92#define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2
93#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000
94#define CONFIG_VERY_BIG_RAM
95
96#define CONFIG_DIMM_SLOTS_PER_CTLR 2
97#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
98
99#if defined(CONFIG_SPD_EEPROM)
100
101
102
103 #define SPD_EEPROM_ADDRESS1 0x51
104 #define SPD_EEPROM_ADDRESS2 0x52
105 #define SPD_EEPROM_ADDRESS3 0x53
106 #define SPD_EEPROM_ADDRESS4 0x54
107
108#else
109
110
111
112
113 #define CONFIG_SYS_SDRAM_SIZE 512
114
115 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
116 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
117 #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000
118 #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000
119 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
120 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
121 #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000
122 #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000
123 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
124 #define CONFIG_SYS_DDR_TIMING_0 0x00220802
125 #define CONFIG_SYS_DDR_TIMING_1 0x38377322
126 #define CONFIG_SYS_DDR_TIMING_2 0x002040c7
127 #define CONFIG_SYS_DDR_CFG_1A 0x43008008
128 #define CONFIG_SYS_DDR_CFG_2 0x24401000
129 #define CONFIG_SYS_DDR_MODE_1 0x23c00542
130 #define CONFIG_SYS_DDR_MODE_2 0x00000000
131 #define CONFIG_SYS_DDR_MODE_CTL 0x00000000
132 #define CONFIG_SYS_DDR_INTERVAL 0x05080100
133 #define CONFIG_SYS_DDR_DATA_INIT 0x00000000
134 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
135 #define CONFIG_SYS_DDR_CFG_1B 0xC3008008
136
137 #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F
138 #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000
139 #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000
140 #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000
141 #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102
142 #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000
143 #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000
144 #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000
145 #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000
146 #define CONFIG_SYS_DDR2_TIMING_0 0x00220802
147 #define CONFIG_SYS_DDR2_TIMING_1 0x38377322
148 #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7
149 #define CONFIG_SYS_DDR2_CFG_1A 0x43008008
150 #define CONFIG_SYS_DDR2_CFG_2 0x24401000
151 #define CONFIG_SYS_DDR2_MODE_1 0x23c00542
152 #define CONFIG_SYS_DDR2_MODE_2 0x00000000
153 #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000
154 #define CONFIG_SYS_DDR2_INTERVAL 0x05080100
155 #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000
156 #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000
157 #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008
158
159#endif
160
161
162
163
164
165
166
167#define CONFIG_SYS_FLASH_BASE 0xff000000
168
169
170#define CONFIG_SYS_BR0_PRELIM 0xff001001
171#define CONFIG_SYS_OR0_PRELIM 0xff006e65
172
173
174#define CONFIG_SYS_BR1_PRELIM 0xf0000801
175#define CONFIG_SYS_OR1_PRELIM 0xffff6e65
176
177
178#define CONFIG_SYS_BR2_PRELIM 0xf1000801
179#define CONFIG_SYS_OR2_PRELIM 0xfff06e65
180
181
182#define CONFIG_SYS_BR3_PRELIM 0xe0001861
183#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0
184#define CONFIG_SYS_BR4_PRELIM 0xe4001861
185#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0
186
187
188#define CONFIG_SYS_BR5_PRELIM 0xe8001001
189#define CONFIG_SYS_OR5_PRELIM 0xf8006e65
190
191
192#define CONFIG_SYS_BR6_PRELIM 0xf4000801
193#define CONFIG_SYS_OR6_PRELIM 0xfff06e65
194
195
196#define CONFIG_SYS_BR7_PRELIM 0xf2000801
197#define CONFIG_SYS_OR7_PRELIM 0xfff06e65
198
199#define CONFIG_SYS_MAX_FLASH_BANKS 1
200#define CONFIG_SYS_MAX_FLASH_SECT 131
201
202#undef CONFIG_SYS_FLASH_CHECKSUM
203#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
204#define CONFIG_SYS_FLASH_WRITE_TOUT 500
205#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
206#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000
207
208#define CONFIG_SYS_WRITE_SWAPPED_DATA
209#define CONFIG_SYS_FLASH_EMPTY_INFO
210
211#undef CONFIG_CLOCKS_IN_MHZ
212
213#define CONFIG_SYS_INIT_RAM_LOCK 1
214#ifndef CONFIG_SYS_INIT_RAM_LOCK
215#define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000
216#else
217#define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000
218#endif
219#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
220
221#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
222#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
223
224#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
225#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
226
227
228#define CONFIG_SYS_NS16550_SERIAL
229#define CONFIG_SYS_NS16550_REG_SIZE 1
230#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
231
232#define CONFIG_SYS_BAUDRATE_TABLE \
233 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
234
235#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
236#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
237
238
239
240
241#define CONFIG_SYS_I2C
242#define CONFIG_SYS_I2C_FSL
243#define CONFIG_SYS_FSL_I2C_SPEED 400000
244#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
245#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
246#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
247
248
249
250
251#define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000
252#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE
253#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000
254
255
256
257
258
259#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
260#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
261#define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS
262#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
263#define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000
264#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS
265#define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS
266#define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000
267
268#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
269#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
270#define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS
271#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
272#define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000
273#define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS
274#define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS
275#define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000
276
277#if defined(CONFIG_PCI)
278
279#define CONFIG_PCI_SCAN_SHOW
280
281#undef CONFIG_EEPRO100
282#undef CONFIG_TULIP
283
284#if !defined(CONFIG_PCI_PNP)
285 #define PCI_ENET0_IOADDR 0xe0000000
286 #define PCI_ENET0_MEMADDR 0xe0000000
287 #define PCI_IDSEL_NUMBER 0x0c
288#endif
289
290#define CONFIG_PCI_SCAN_SHOW
291
292#ifdef CONFIG_SCSI_AHCI
293#define CONFIG_SATA_ULI5288
294#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
295#define CONFIG_SYS_SCSI_MAX_LUN 1
296#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
297#endif
298
299#endif
300
301#if defined(CONFIG_TSEC_ENET)
302#define CONFIG_TSEC1 1
303#define CONFIG_TSEC1_NAME "eTSEC1"
304#define CONFIG_TSEC2 1
305#define CONFIG_TSEC2_NAME "eTSEC2"
306#define CONFIG_TSEC3 1
307#define CONFIG_TSEC3_NAME "eTSEC3"
308#define CONFIG_TSEC4 1
309#define CONFIG_TSEC4_NAME "eTSEC4"
310
311#define TSEC1_PHY_ADDR 0x1F
312#define TSEC2_PHY_ADDR 0x00
313#define TSEC3_PHY_ADDR 0x01
314#define TSEC4_PHY_ADDR 0x02
315#define TSEC1_PHYIDX 0
316#define TSEC2_PHYIDX 0
317#define TSEC3_PHYIDX 0
318#define TSEC4_PHYIDX 0
319#define TSEC1_FLAGS TSEC_GIGABIT
320#define TSEC2_FLAGS TSEC_GIGABIT
321#define TSEC3_FLAGS TSEC_GIGABIT
322#define TSEC4_FLAGS TSEC_GIGABIT
323
324#define CONFIG_SYS_TBIPA_VALUE 0x1e
325
326#define CONFIG_ETHPRIME "eTSEC1"
327
328#endif
329
330
331
332
333
334#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
335#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
336#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
337#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
338
339
340
341
342
343
344
345#define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \
346 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
347#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP)
348#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
349#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
350
351
352
353
354
355#define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \
356 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
357#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
358#define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
359#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
360
361
362
363
364
365#define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
366 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
367#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
368#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
369#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
370
371#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
372#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
373 | BATL_PP_RW | BATL_CACHEINHIBIT \
374 | BATL_GUARDEDSTORAGE)
375#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
376 | BATU_BL_1M | BATU_VS | BATU_VP)
377#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
378 | BATL_PP_RW | BATL_CACHEINHIBIT)
379#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
380#endif
381
382
383
384
385
386
387
388#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \
389 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
390#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP)
391#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
392#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
393
394
395
396
397
398#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
399#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
400#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
401#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
402
403
404
405
406
407#define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
408 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
409#define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
410#define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
411#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
412
413
414#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
415 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
416#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
417#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
418 | BATL_MEMCOHERENCE)
419#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
420
421#define CONFIG_SYS_DBAT7L 0x00000000
422#define CONFIG_SYS_DBAT7U 0x00000000
423#define CONFIG_SYS_IBAT7L 0x00000000
424#define CONFIG_SYS_IBAT7U 0x00000000
425
426
427
428
429#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
430#define CONFIG_ENV_SECT_SIZE 0x20000
431#define CONFIG_ENV_SIZE 0x2000
432
433#define CONFIG_LOADS_ECHO 1
434#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
435
436#undef CONFIG_WATCHDOG
437
438
439
440
441#define CONFIG_SYS_LOAD_ADDR 0x2000000
442
443
444
445
446
447
448#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
449
450
451#define CONFIG_SYS_DCACHE_SIZE 32768
452#define CONFIG_SYS_CACHELINE_SIZE 32
453#if defined(CONFIG_CMD_KGDB)
454#define CONFIG_SYS_CACHELINE_SHIFT 5
455#endif
456
457#if defined(CONFIG_CMD_KGDB)
458#define CONFIG_KGDB_BAUDRATE 230400
459#endif
460
461
462
463
464
465#define CONFIG_HAS_ETH0 1
466#define CONFIG_HAS_ETH1 1
467#define CONFIG_HAS_ETH2 1
468#define CONFIG_HAS_ETH3 1
469
470#define CONFIG_IPADDR 192.168.0.50
471
472#define CONFIG_HOSTNAME "sbc8641d"
473#define CONFIG_ROOTPATH "/opt/eldk/ppc_74xx"
474#define CONFIG_BOOTFILE "uImage"
475
476#define CONFIG_SERVERIP 192.168.0.2
477#define CONFIG_GATEWAYIP 192.168.0.1
478#define CONFIG_NETMASK 255.255.255.0
479
480
481#define CONFIG_LOADADDR 1000000
482
483#define CONFIG_EXTRA_ENV_SETTINGS \
484 "netdev=eth0\0" \
485 "consoledev=ttyS0\0" \
486 "ramdiskaddr=2000000\0" \
487 "ramdiskfile=uRamdisk\0" \
488 "dtbaddr=400000\0" \
489 "dtbfile=sbc8641d.dtb\0" \
490 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
491 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
492 "maxcpus=1"
493
494#define CONFIG_NFSBOOTCOMMAND \
495 "setenv bootargs root=/dev/nfs rw " \
496 "nfsroot=$serverip:$rootpath " \
497 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
498 "console=$consoledev,$baudrate $othbootargs;" \
499 "tftp $loadaddr $bootfile;" \
500 "tftp $dtbaddr $dtbfile;" \
501 "bootm $loadaddr - $dtbaddr"
502
503#define CONFIG_RAMBOOTCOMMAND \
504 "setenv bootargs root=/dev/ram rw " \
505 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
506 "console=$consoledev,$baudrate $othbootargs;" \
507 "tftp $ramdiskaddr $ramdiskfile;" \
508 "tftp $loadaddr $bootfile;" \
509 "tftp $dtbaddr $dtbfile;" \
510 "bootm $loadaddr $ramdiskaddr $dtbaddr"
511
512#define CONFIG_FLASHBOOTCOMMAND \
513 "setenv bootargs root=/dev/ram rw " \
514 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
515 "console=$consoledev,$baudrate $othbootargs;" \
516 "bootm ffd00000 ffb00000 ffa00000"
517
518#define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND
519
520#endif
521