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11#ifndef __TISCI_PROTOCOL_H
12#define __TISCI_PROTOCOL_H
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23struct ti_sci_version_info {
24 u8 abi_major;
25 u8 abi_minor;
26 u16 firmware_revision;
27 char firmware_description[32];
28};
29
30struct ti_sci_handle;
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49struct ti_sci_board_ops {
50 int (*board_config)(const struct ti_sci_handle *handle,
51 u64 addr, u32 size);
52 int (*board_config_rm)(const struct ti_sci_handle *handle,
53 u64 addr, u32 size);
54 int (*board_config_security)(const struct ti_sci_handle *handle,
55 u64 addr, u32 size);
56 int (*board_config_pm)(const struct ti_sci_handle *handle,
57 u64 addr, u32 size);
58};
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121struct ti_sci_dev_ops {
122 int (*get_device)(const struct ti_sci_handle *handle, u32 id);
123 int (*get_device_exclusive)(const struct ti_sci_handle *handle, u32 id);
124 int (*idle_device)(const struct ti_sci_handle *handle, u32 id);
125 int (*idle_device_exclusive)(const struct ti_sci_handle *handle,
126 u32 id);
127 int (*put_device)(const struct ti_sci_handle *handle, u32 id);
128 int (*is_valid)(const struct ti_sci_handle *handle, u32 id);
129 int (*get_context_loss_count)(const struct ti_sci_handle *handle,
130 u32 id, u32 *count);
131 int (*is_idle)(const struct ti_sci_handle *handle, u32 id,
132 bool *requested_state);
133 int (*is_stop)(const struct ti_sci_handle *handle, u32 id,
134 bool *req_state, bool *current_state);
135 int (*is_on)(const struct ti_sci_handle *handle, u32 id,
136 bool *req_state, bool *current_state);
137 int (*is_transitioning)(const struct ti_sci_handle *handle, u32 id,
138 bool *current_state);
139 int (*set_device_resets)(const struct ti_sci_handle *handle, u32 id,
140 u32 reset_state);
141 int (*get_device_resets)(const struct ti_sci_handle *handle, u32 id,
142 u32 *reset_state);
143 int (*release_exclusive_devices)(const struct ti_sci_handle *handle);
144};
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195struct ti_sci_clk_ops {
196 int (*get_clock)(const struct ti_sci_handle *handle, u32 did, u8 cid,
197 bool needs_ssc, bool can_change_freq,
198 bool enable_input_term);
199 int (*idle_clock)(const struct ti_sci_handle *handle, u32 did, u8 cid);
200 int (*put_clock)(const struct ti_sci_handle *handle, u32 did, u8 cid);
201 int (*is_auto)(const struct ti_sci_handle *handle, u32 did, u8 cid,
202 bool *req_state);
203 int (*is_on)(const struct ti_sci_handle *handle, u32 did, u8 cid,
204 bool *req_state, bool *current_state);
205 int (*is_off)(const struct ti_sci_handle *handle, u32 did, u8 cid,
206 bool *req_state, bool *current_state);
207 int (*set_parent)(const struct ti_sci_handle *handle, u32 did, u8 cid,
208 u8 parent_id);
209 int (*get_parent)(const struct ti_sci_handle *handle, u32 did, u8 cid,
210 u8 *parent_id);
211 int (*get_num_parents)(const struct ti_sci_handle *handle, u32 did,
212 u8 cid, u8 *num_parents);
213 int (*get_best_match_freq)(const struct ti_sci_handle *handle, u32 did,
214 u8 cid, u64 min_freq, u64 target_freq,
215 u64 max_freq, u64 *match_freq);
216 int (*set_freq)(const struct ti_sci_handle *handle, u32 did, u8 cid,
217 u64 min_freq, u64 target_freq, u64 max_freq);
218 int (*get_freq)(const struct ti_sci_handle *handle, u32 did, u8 cid,
219 u64 *current_freq);
220};
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239struct ti_sci_rm_core_ops {
240 int (*get_range)(const struct ti_sci_handle *handle, u32 dev_id,
241 u8 subtype, u16 *range_start, u16 *range_num);
242 int (*get_range_from_shost)(const struct ti_sci_handle *handle,
243 u32 dev_id, u8 subtype, u8 s_host,
244 u16 *range_start, u16 *range_num);
245};
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255struct ti_sci_core_ops {
256 int (*reboot_device)(const struct ti_sci_handle *handle);
257 int (*query_msmc)(const struct ti_sci_handle *handle,
258 u64 *msmc_start, u64 *msmc_end);
259};
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282struct ti_sci_proc_ops {
283 int (*proc_request)(const struct ti_sci_handle *handle, u8 pid);
284 int (*proc_release)(const struct ti_sci_handle *handle, u8 pid);
285 int (*proc_handover)(const struct ti_sci_handle *handle, u8 pid,
286 u8 hid);
287 int (*set_proc_boot_cfg)(const struct ti_sci_handle *handle, u8 pid,
288 u64 bv, u32 cfg_set, u32 cfg_clr);
289 int (*set_proc_boot_ctrl)(const struct ti_sci_handle *handle, u8 pid,
290 u32 ctrl_set, u32 ctrl_clr);
291 int (*proc_auth_boot_image)(const struct ti_sci_handle *handle,
292 u64 *image_addr, u32 *image_size);
293 int (*get_proc_boot_status)(const struct ti_sci_handle *handle, u8 pid,
294 u64 *bv, u32 *cfg_flags, u32 *ctrl_flags,
295 u32 *sts_flags);
296 int (*proc_shutdown_no_wait)(const struct ti_sci_handle *handle,
297 u8 pid);
298};
299
300#define TI_SCI_RING_MODE_RING (0)
301#define TI_SCI_RING_MODE_MESSAGE (1)
302#define TI_SCI_RING_MODE_CREDENTIALS (2)
303#define TI_SCI_RING_MODE_QM (3)
304
305#define TI_SCI_MSG_UNUSED_SECONDARY_HOST TI_SCI_RM_NULL_U8
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308#define TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID BIT(0)
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310#define TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID BIT(1)
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312#define TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID BIT(2)
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314#define TI_SCI_MSG_VALUE_RM_RING_MODE_VALID BIT(3)
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316#define TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID BIT(4)
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318#define TI_SCI_MSG_VALUE_RM_RING_ORDER_ID_VALID BIT(5)
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320#define TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER \
321 (TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID | \
322 TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID | \
323 TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID | \
324 TI_SCI_MSG_VALUE_RM_RING_MODE_VALID | \
325 TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID)
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333struct ti_sci_rm_ringacc_ops {
334 int (*config)(const struct ti_sci_handle *handle,
335 u32 valid_params, u16 nav_id, u16 index,
336 u32 addr_lo, u32 addr_hi, u32 count, u8 mode,
337 u8 size, u8 order_id
338 );
339 int (*get_config)(const struct ti_sci_handle *handle,
340 u32 nav_id, u32 index, u8 *mode,
341 u32 *addr_lo, u32 *addr_hi, u32 *count,
342 u8 *size, u8 *order_id);
343};
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358struct ti_sci_rm_psil_ops {
359 int (*pair)(const struct ti_sci_handle *handle, u32 nav_id,
360 u32 src_thread, u32 dst_thread);
361 int (*unpair)(const struct ti_sci_handle *handle, u32 nav_id,
362 u32 src_thread, u32 dst_thread);
363};
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365
366#define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR 2
367#define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR_SB 3
368#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBRR 10
369#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBVR 11
370#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR 12
371#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBVR 13
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374#define TI_SCI_RM_UDMAP_ATYPE_PHYS 0
375#define TI_SCI_RM_UDMAP_ATYPE_INTERMEDIATE 1
376#define TI_SCI_RM_UDMAP_ATYPE_VIRTUAL 2
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379#define TI_SCI_RM_UDMAP_SCHED_PRIOR_HIGH 0
380#define TI_SCI_RM_UDMAP_SCHED_PRIOR_MEDHIGH 1
381#define TI_SCI_RM_UDMAP_SCHED_PRIOR_MEDLOW 2
382#define TI_SCI_RM_UDMAP_SCHED_PRIOR_LOW 3
383
384#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST 0
385#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_MONO 2
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388#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID BIT(0)
389#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID BIT(1)
390#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID BIT(2)
391#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID BIT(3)
392#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID BIT(4)
393#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_VALID BIT(5)
394#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID BIT(6)
395#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID BIT(7)
396#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID BIT(8)
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404struct ti_sci_msg_rm_udmap_tx_ch_cfg {
405 u32 valid_params;
406#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID BIT(9)
407#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID BIT(10)
408#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID BIT(11)
409#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID BIT(12)
410#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID BIT(13)
411 u16 nav_id;
412 u16 index;
413 u8 tx_pause_on_err;
414 u8 tx_filt_einfo;
415 u8 tx_filt_pswords;
416 u8 tx_atype;
417 u8 tx_chan_type;
418 u8 tx_supr_tdpkt;
419 u16 tx_fetch_size;
420 u8 tx_credit_count;
421 u16 txcq_qnum;
422 u8 tx_priority;
423 u8 tx_qos;
424 u8 tx_orderid;
425 u16 fdepth;
426 u8 tx_sched_priority;
427};
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435struct ti_sci_msg_rm_udmap_rx_ch_cfg {
436 u32 valid_params;
437#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID BIT(9)
438#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID BIT(10)
439#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID BIT(11)
440#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID BIT(12)
441 u16 nav_id;
442 u16 index;
443 u16 rx_fetch_size;
444 u16 rxcq_qnum;
445 u8 rx_priority;
446 u8 rx_qos;
447 u8 rx_orderid;
448 u8 rx_sched_priority;
449 u16 flowid_start;
450 u16 flowid_cnt;
451 u8 rx_pause_on_err;
452 u8 rx_atype;
453 u8 rx_chan_type;
454 u8 rx_ignore_short;
455 u8 rx_ignore_long;
456};
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464struct ti_sci_msg_rm_udmap_flow_cfg {
465 u32 valid_params;
466#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID BIT(0)
467#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID BIT(1)
468#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID BIT(2)
469#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID BIT(3)
470#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SOP_OFFSET_VALID BIT(4)
471#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID BIT(5)
472#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_VALID BIT(6)
473#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_VALID BIT(7)
474#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_VALID BIT(8)
475#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_VALID BIT(9)
476#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID BIT(10)
477#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID BIT(11)
478#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID BIT(12)
479#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID BIT(13)
480#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID BIT(14)
481#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID BIT(15)
482#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID BIT(16)
483#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID BIT(17)
484#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID BIT(18)
485 u16 nav_id;
486 u16 flow_index;
487 u8 rx_einfo_present;
488 u8 rx_psinfo_present;
489 u8 rx_error_handling;
490 u8 rx_desc_type;
491 u16 rx_sop_offset;
492 u16 rx_dest_qnum;
493 u8 rx_src_tag_hi;
494 u8 rx_src_tag_lo;
495 u8 rx_dest_tag_hi;
496 u8 rx_dest_tag_lo;
497 u8 rx_src_tag_hi_sel;
498 u8 rx_src_tag_lo_sel;
499 u8 rx_dest_tag_hi_sel;
500 u8 rx_dest_tag_lo_sel;
501 u16 rx_fdq0_sz0_qnum;
502 u16 rx_fdq1_qnum;
503 u16 rx_fdq2_qnum;
504 u16 rx_fdq3_qnum;
505 u8 rx_ps_location;
506};
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514struct ti_sci_rm_udmap_ops {
515 int (*tx_ch_cfg)(const struct ti_sci_handle *handle,
516 const struct ti_sci_msg_rm_udmap_tx_ch_cfg *params);
517 int (*rx_ch_cfg)(const struct ti_sci_handle *handle,
518 const struct ti_sci_msg_rm_udmap_rx_ch_cfg *params);
519 int (*rx_flow_cfg)(
520 const struct ti_sci_handle *handle,
521 const struct ti_sci_msg_rm_udmap_flow_cfg *params);
522};
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540struct ti_sci_msg_fwl_region {
541 u16 fwl_id;
542 u16 region;
543 u32 n_permission_regs;
544 u32 control;
545 u32 permissions[3];
546 u64 start_address;
547 u64 end_address;
548} __packed;
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566struct ti_sci_msg_fwl_owner {
567 u16 fwl_id;
568 u16 region;
569 u8 owner_index;
570 u8 owner_privid;
571 u16 owner_permission_bits;
572} __packed;
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580struct ti_sci_fwl_ops {
581 int (*set_fwl_region)(const struct ti_sci_handle *handle, const struct ti_sci_msg_fwl_region *region);
582 int (*get_fwl_region)(const struct ti_sci_handle *handle, struct ti_sci_msg_fwl_region *region);
583 int (*change_fwl_owner)(const struct ti_sci_handle *handle, struct ti_sci_msg_fwl_owner *owner);
584};
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596struct ti_sci_ops {
597 struct ti_sci_board_ops board_ops;
598 struct ti_sci_dev_ops dev_ops;
599 struct ti_sci_clk_ops clk_ops;
600 struct ti_sci_core_ops core_ops;
601 struct ti_sci_proc_ops proc_ops;
602 struct ti_sci_rm_core_ops rm_core_ops;
603 struct ti_sci_rm_ringacc_ops rm_ring_ops;
604 struct ti_sci_rm_psil_ops rm_psil_ops;
605 struct ti_sci_rm_udmap_ops rm_udmap_ops;
606 struct ti_sci_fwl_ops fwl_ops;
607};
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614struct ti_sci_handle {
615 struct ti_sci_ops ops;
616 struct ti_sci_version_info version;
617};
618
619#define TI_SCI_RESOURCE_NULL 0xffff
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627struct ti_sci_resource_desc {
628 u16 start;
629 u16 num;
630 unsigned long *res_map;
631};
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639struct ti_sci_resource {
640 u16 sets;
641 struct ti_sci_resource_desc *desc;
642};
643
644#if IS_ENABLED(CONFIG_TI_SCI_PROTOCOL)
645
646const struct ti_sci_handle *ti_sci_get_handle_from_sysfw(struct udevice *dev);
647const struct ti_sci_handle *ti_sci_get_handle(struct udevice *dev);
648const struct ti_sci_handle *ti_sci_get_by_phandle(struct udevice *dev,
649 const char *property);
650u16 ti_sci_get_free_resource(struct ti_sci_resource *res);
651void ti_sci_release_resource(struct ti_sci_resource *res, u16 id);
652struct ti_sci_resource *
653devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
654 struct udevice *dev, u32 dev_id, char *of_prop);
655
656#else
657
658static inline
659const struct ti_sci_handle *ti_sci_get_handle_from_sysfw(struct udevice *dev)
660{
661 return ERR_PTR(-EINVAL);
662}
663
664static inline const struct ti_sci_handle *ti_sci_get_handle(struct udevice *dev)
665{
666 return ERR_PTR(-EINVAL);
667}
668
669static inline
670const struct ti_sci_handle *ti_sci_get_by_phandle(struct udevice *dev,
671 const char *property)
672{
673 return ERR_PTR(-EINVAL);
674}
675
676static inline u16 ti_sci_get_free_resource(struct ti_sci_resource *res)
677{
678 return TI_SCI_RESOURCE_NULL;
679}
680
681static inline void ti_sci_release_resource(struct ti_sci_resource *res, u16 id)
682{
683}
684
685static inline struct ti_sci_resource *
686devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
687 struct udevice *dev, u32 dev_id, char *of_prop)
688{
689 return ERR_PTR(-EINVAL);
690}
691#endif
692
693#endif
694