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9#ifndef __SDHCI_HW_H
10#define __SDHCI_HW_H
11
12#include <asm/io.h>
13#include <mmc.h>
14#include <asm/gpio.h>
15
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18
19
20#define SDHCI_DMA_ADDRESS 0x00
21
22#define SDHCI_BLOCK_SIZE 0x04
23#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
24
25#define SDHCI_BLOCK_COUNT 0x06
26
27#define SDHCI_ARGUMENT 0x08
28
29#define SDHCI_TRANSFER_MODE 0x0C
30#define SDHCI_TRNS_DMA BIT(0)
31#define SDHCI_TRNS_BLK_CNT_EN BIT(1)
32#define SDHCI_TRNS_ACMD12 BIT(2)
33#define SDHCI_TRNS_READ BIT(4)
34#define SDHCI_TRNS_MULTI BIT(5)
35
36#define SDHCI_COMMAND 0x0E
37#define SDHCI_CMD_RESP_MASK 0x03
38#define SDHCI_CMD_CRC 0x08
39#define SDHCI_CMD_INDEX 0x10
40#define SDHCI_CMD_DATA 0x20
41#define SDHCI_CMD_ABORTCMD 0xC0
42
43#define SDHCI_CMD_RESP_NONE 0x00
44#define SDHCI_CMD_RESP_LONG 0x01
45#define SDHCI_CMD_RESP_SHORT 0x02
46#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
47
48#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
49#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
50
51#define SDHCI_RESPONSE 0x10
52
53#define SDHCI_BUFFER 0x20
54
55#define SDHCI_PRESENT_STATE 0x24
56#define SDHCI_CMD_INHIBIT BIT(0)
57#define SDHCI_DATA_INHIBIT BIT(1)
58#define SDHCI_DOING_WRITE BIT(8)
59#define SDHCI_DOING_READ BIT(9)
60#define SDHCI_SPACE_AVAILABLE BIT(10)
61#define SDHCI_DATA_AVAILABLE BIT(11)
62#define SDHCI_CARD_PRESENT BIT(16)
63#define SDHCI_CARD_STATE_STABLE BIT(17)
64#define SDHCI_CARD_DETECT_PIN_LEVEL BIT(18)
65#define SDHCI_WRITE_PROTECT BIT(19)
66
67#define SDHCI_HOST_CONTROL 0x28
68#define SDHCI_CTRL_LED BIT(0)
69#define SDHCI_CTRL_4BITBUS BIT(1)
70#define SDHCI_CTRL_HISPD BIT(2)
71#define SDHCI_CTRL_DMA_MASK 0x18
72#define SDHCI_CTRL_SDMA 0x00
73#define SDHCI_CTRL_ADMA1 0x08
74#define SDHCI_CTRL_ADMA32 0x10
75#define SDHCI_CTRL_ADMA64 0x18
76#define SDHCI_CTRL_8BITBUS BIT(5)
77#define SDHCI_CTRL_CD_TEST_INS BIT(6)
78#define SDHCI_CTRL_CD_TEST BIT(7)
79
80#define SDHCI_POWER_CONTROL 0x29
81#define SDHCI_POWER_ON 0x01
82#define SDHCI_POWER_180 0x0A
83#define SDHCI_POWER_300 0x0C
84#define SDHCI_POWER_330 0x0E
85
86#define SDHCI_BLOCK_GAP_CONTROL 0x2A
87
88#define SDHCI_WAKE_UP_CONTROL 0x2B
89#define SDHCI_WAKE_ON_INT BIT(0)
90#define SDHCI_WAKE_ON_INSERT BIT(1)
91#define SDHCI_WAKE_ON_REMOVE BIT(2)
92
93#define SDHCI_CLOCK_CONTROL 0x2C
94#define SDHCI_DIVIDER_SHIFT 8
95#define SDHCI_DIVIDER_HI_SHIFT 6
96#define SDHCI_DIV_MASK 0xFF
97#define SDHCI_DIV_MASK_LEN 8
98#define SDHCI_DIV_HI_MASK 0x300
99#define SDHCI_PROG_CLOCK_MODE BIT(5)
100#define SDHCI_CLOCK_CARD_EN BIT(2)
101#define SDHCI_CLOCK_INT_STABLE BIT(1)
102#define SDHCI_CLOCK_INT_EN BIT(0)
103
104#define SDHCI_TIMEOUT_CONTROL 0x2E
105
106#define SDHCI_SOFTWARE_RESET 0x2F
107#define SDHCI_RESET_ALL 0x01
108#define SDHCI_RESET_CMD 0x02
109#define SDHCI_RESET_DATA 0x04
110
111#define SDHCI_INT_STATUS 0x30
112#define SDHCI_INT_ENABLE 0x34
113#define SDHCI_SIGNAL_ENABLE 0x38
114#define SDHCI_INT_RESPONSE BIT(0)
115#define SDHCI_INT_DATA_END BIT(1)
116#define SDHCI_INT_DMA_END BIT(3)
117#define SDHCI_INT_SPACE_AVAIL BIT(4)
118#define SDHCI_INT_DATA_AVAIL BIT(5)
119#define SDHCI_INT_CARD_INSERT BIT(6)
120#define SDHCI_INT_CARD_REMOVE BIT(7)
121#define SDHCI_INT_CARD_INT BIT(8)
122#define SDHCI_INT_ERROR BIT(15)
123#define SDHCI_INT_TIMEOUT BIT(16)
124#define SDHCI_INT_CRC BIT(17)
125#define SDHCI_INT_END_BIT BIT(18)
126#define SDHCI_INT_INDEX BIT(19)
127#define SDHCI_INT_DATA_TIMEOUT BIT(20)
128#define SDHCI_INT_DATA_CRC BIT(21)
129#define SDHCI_INT_DATA_END_BIT BIT(22)
130#define SDHCI_INT_BUS_POWER BIT(23)
131#define SDHCI_INT_ACMD12ERR BIT(24)
132#define SDHCI_INT_ADMA_ERROR BIT(25)
133
134#define SDHCI_INT_NORMAL_MASK 0x00007FFF
135#define SDHCI_INT_ERROR_MASK 0xFFFF8000
136
137#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
138 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
139#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
140 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
141 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
142 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
143#define SDHCI_INT_ALL_MASK ((unsigned int)-1)
144
145#define SDHCI_ACMD12_ERR 0x3C
146
147#define SDHCI_HOST_CONTROL2 0x3E
148#define SDHCI_CTRL_UHS_MASK 0x0007
149#define SDHCI_CTRL_UHS_SDR12 0x0000
150#define SDHCI_CTRL_UHS_SDR25 0x0001
151#define SDHCI_CTRL_UHS_SDR50 0x0002
152#define SDHCI_CTRL_UHS_SDR104 0x0003
153#define SDHCI_CTRL_UHS_DDR50 0x0004
154#define SDHCI_CTRL_HS400 0x0005
155#define SDHCI_CTRL_VDD_180 0x0008
156#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
157#define SDHCI_CTRL_DRV_TYPE_B 0x0000
158#define SDHCI_CTRL_DRV_TYPE_A 0x0010
159#define SDHCI_CTRL_DRV_TYPE_C 0x0020
160#define SDHCI_CTRL_DRV_TYPE_D 0x0030
161#define SDHCI_CTRL_EXEC_TUNING 0x0040
162#define SDHCI_CTRL_TUNED_CLK 0x0080
163#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
164
165#define SDHCI_CAPABILITIES 0x40
166#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
167#define SDHCI_TIMEOUT_CLK_SHIFT 0
168#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
169#define SDHCI_CLOCK_BASE_MASK 0x00003F00
170#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
171#define SDHCI_CLOCK_BASE_SHIFT 8
172#define SDHCI_MAX_BLOCK_MASK 0x00030000
173#define SDHCI_MAX_BLOCK_SHIFT 16
174#define SDHCI_CAN_DO_8BIT BIT(18)
175#define SDHCI_CAN_DO_ADMA2 BIT(19)
176#define SDHCI_CAN_DO_ADMA1 BIT(20)
177#define SDHCI_CAN_DO_HISPD BIT(21)
178#define SDHCI_CAN_DO_SDMA BIT(22)
179#define SDHCI_CAN_VDD_330 BIT(24)
180#define SDHCI_CAN_VDD_300 BIT(25)
181#define SDHCI_CAN_VDD_180 BIT(26)
182#define SDHCI_CAN_64BIT BIT(28)
183
184#define SDHCI_CAPABILITIES_1 0x44
185#define SDHCI_SUPPORT_SDR50 0x00000001
186#define SDHCI_SUPPORT_SDR104 0x00000002
187#define SDHCI_SUPPORT_DDR50 0x00000004
188#define SDHCI_USE_SDR50_TUNING 0x00002000
189
190#define SDHCI_CLOCK_MUL_MASK 0x00FF0000
191#define SDHCI_CLOCK_MUL_SHIFT 16
192
193#define SDHCI_MAX_CURRENT 0x48
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197#define SDHCI_SET_ACMD12_ERROR 0x50
198#define SDHCI_SET_INT_ERROR 0x52
199
200#define SDHCI_ADMA_ERROR 0x54
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204#define SDHCI_ADMA_ADDRESS 0x58
205#define SDHCI_ADMA_ADDRESS_HI 0x5c
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207
208
209#define SDHCI_SLOT_INT_STATUS 0xFC
210
211#define SDHCI_HOST_VERSION 0xFE
212#define SDHCI_VENDOR_VER_MASK 0xFF00
213#define SDHCI_VENDOR_VER_SHIFT 8
214#define SDHCI_SPEC_VER_MASK 0x00FF
215#define SDHCI_SPEC_VER_SHIFT 0
216#define SDHCI_SPEC_100 0
217#define SDHCI_SPEC_200 1
218#define SDHCI_SPEC_300 2
219
220#define SDHCI_GET_VERSION(x) (x->version & SDHCI_SPEC_VER_MASK)
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225
226#define SDHCI_MAX_DIV_SPEC_200 256
227#define SDHCI_MAX_DIV_SPEC_300 2046
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231
232#define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 0)
233#define SDHCI_QUIRK_REG32_RW (1 << 1)
234#define SDHCI_QUIRK_BROKEN_R1B (1 << 2)
235#define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3)
236#define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4)
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241
242#define SDHCI_QUIRK_BROKEN_HISPD_MODE BIT(5)
243#define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6)
244#define SDHCI_QUIRK_USE_WIDE8 (1 << 8)
245#define SDHCI_QUIRK_NO_1_8_V (1 << 9)
246
247
248struct sdhci_host;
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252
253#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
254#define SDHCI_DEFAULT_BOUNDARY_ARG (7)
255struct sdhci_ops {
256#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
257 u32 (*read_l)(struct sdhci_host *host, int reg);
258 u16 (*read_w)(struct sdhci_host *host, int reg);
259 u8 (*read_b)(struct sdhci_host *host, int reg);
260 void (*write_l)(struct sdhci_host *host, u32 val, int reg);
261 void (*write_w)(struct sdhci_host *host, u16 val, int reg);
262 void (*write_b)(struct sdhci_host *host, u8 val, int reg);
263#endif
264 int (*get_cd)(struct sdhci_host *host);
265 void (*set_control_reg)(struct sdhci_host *host);
266 int (*set_ios_post)(struct sdhci_host *host);
267 void (*set_clock)(struct sdhci_host *host, u32 div);
268 int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
269 void (*set_delay)(struct sdhci_host *host);
270};
271
272#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
273#define ADMA_MAX_LEN 65532
274#ifdef CONFIG_DMA_ADDR_T_64BIT
275#define ADMA_DESC_LEN 16
276#else
277#define ADMA_DESC_LEN 8
278#endif
279#define ADMA_TABLE_NO_ENTRIES (CONFIG_SYS_MMC_MAX_BLK_COUNT * \
280 MMC_MAX_BLOCK_LEN) / ADMA_MAX_LEN
281
282#define ADMA_TABLE_SZ (ADMA_TABLE_NO_ENTRIES * ADMA_DESC_LEN)
283
284
285#define ADMA_DESC_ATTR_VALID BIT(0)
286#define ADMA_DESC_ATTR_END BIT(1)
287#define ADMA_DESC_ATTR_INT BIT(2)
288#define ADMA_DESC_ATTR_ACT1 BIT(4)
289#define ADMA_DESC_ATTR_ACT2 BIT(5)
290
291#define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
292#define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
293
294struct sdhci_adma_desc {
295 u8 attr;
296 u8 reserved;
297 u16 len;
298 u32 addr_lo;
299#ifdef CONFIG_DMA_ADDR_T_64BIT
300 u32 addr_hi;
301#endif
302} __packed;
303#endif
304struct sdhci_host {
305 const char *name;
306 void *ioaddr;
307 unsigned int quirks;
308 unsigned int host_caps;
309 unsigned int version;
310 unsigned int max_clk;
311 unsigned int clk_mul;
312 unsigned int clock;
313 struct mmc *mmc;
314 const struct sdhci_ops *ops;
315 int index;
316
317 int bus_width;
318 struct gpio_desc pwr_gpio;
319 struct gpio_desc cd_gpio;
320
321 uint voltages;
322
323 struct mmc_config cfg;
324 dma_addr_t start_addr;
325 int flags;
326#define USE_SDMA (0x1 << 0)
327#define USE_ADMA (0x1 << 1)
328#define USE_ADMA64 (0x1 << 2)
329#define USE_DMA (USE_SDMA | USE_ADMA | USE_ADMA64)
330 dma_addr_t adma_addr;
331#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
332 struct sdhci_adma_desc *adma_desc_table;
333 uint desc_slot;
334#endif
335};
336
337#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
338
339static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
340{
341 if (unlikely(host->ops->write_l))
342 host->ops->write_l(host, val, reg);
343 else
344 writel(val, host->ioaddr + reg);
345}
346
347static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
348{
349 if (unlikely(host->ops->write_w))
350 host->ops->write_w(host, val, reg);
351 else
352 writew(val, host->ioaddr + reg);
353}
354
355static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
356{
357 if (unlikely(host->ops->write_b))
358 host->ops->write_b(host, val, reg);
359 else
360 writeb(val, host->ioaddr + reg);
361}
362
363static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
364{
365 if (unlikely(host->ops->read_l))
366 return host->ops->read_l(host, reg);
367 else
368 return readl(host->ioaddr + reg);
369}
370
371static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
372{
373 if (unlikely(host->ops->read_w))
374 return host->ops->read_w(host, reg);
375 else
376 return readw(host->ioaddr + reg);
377}
378
379static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
380{
381 if (unlikely(host->ops->read_b))
382 return host->ops->read_b(host, reg);
383 else
384 return readb(host->ioaddr + reg);
385}
386
387#else
388
389static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
390{
391 writel(val, host->ioaddr + reg);
392}
393
394static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
395{
396 writew(val, host->ioaddr + reg);
397}
398
399static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
400{
401 writeb(val, host->ioaddr + reg);
402}
403static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
404{
405 return readl(host->ioaddr + reg);
406}
407
408static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
409{
410 return readw(host->ioaddr + reg);
411}
412
413static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
414{
415 return readb(host->ioaddr + reg);
416}
417#endif
418
419#ifdef CONFIG_BLK
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452int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
453 u32 f_max, u32 f_min);
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470int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
471#else
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483int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min);
484#endif
485
486void sdhci_set_uhs_timing(struct sdhci_host *host);
487#ifdef CONFIG_DM_MMC
488
489int sdhci_probe(struct udevice *dev);
490int sdhci_set_clock(struct mmc *mmc, unsigned int clock);
491extern const struct dm_mmc_ops sdhci_ops;
492#else
493#endif
494
495#endif
496