LXR uboot/arch/arm/include/asm/arch-lpc32xx/config.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Common definitions for LPC32XX board configurations
   4 *
   5 * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
   6 */
   7
   8#ifndef _LPC32XX_CONFIG_H
   9#define _LPC32XX_CONFIG_H
  10
  11
  12/* Basic CPU architecture */
  13
  14/* UART configuration */
  15#if     (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \
  16        (CONFIG_SYS_LPC32XX_UART == 7)
  17#if !defined(CONFIG_LPC32XX_HSUART)
  18#define CONFIG_LPC32XX_HSUART
  19#endif
  20#endif
  21
  22#if !defined(CONFIG_SYS_NS16550_CLK)
  23#define CONFIG_SYS_NS16550_CLK          13000000
  24#endif
  25
  26#define CONFIG_SYS_BAUDRATE_TABLE       \
  27                { 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
  28
  29/* Ethernet */
  30#define LPC32XX_ETH_BASE ETHERNET_BASE
  31
  32/* NAND */
  33#if defined(CONFIG_NAND_LPC32XX_SLC)
  34#define NAND_LARGE_BLOCK_PAGE_SIZE      0x800
  35#define NAND_SMALL_BLOCK_PAGE_SIZE      0x200
  36
  37#if !defined(CONFIG_SYS_NAND_PAGE_SIZE)
  38#define CONFIG_SYS_NAND_PAGE_SIZE       NAND_LARGE_BLOCK_PAGE_SIZE
  39#endif
  40
  41#if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE)
  42#define CONFIG_SYS_NAND_OOBSIZE         64
  43#define CONFIG_SYS_NAND_ECCPOS          { 40, 41, 42, 43, 44, 45, 46, 47, \
  44                                          48, 49, 50, 51, 52, 53, 54, 55, \
  45                                          56, 57, 58, 59, 60, 61, 62, 63, }
  46#define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
  47#elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE)
  48#define CONFIG_SYS_NAND_OOBSIZE         16
  49#define CONFIG_SYS_NAND_ECCPOS          { 10, 11, 12, 13, 14, 15, }
  50#define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
  51#else
  52#error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value"
  53#endif
  54
  55#define CONFIG_SYS_NAND_ECCSIZE         0x100
  56#define CONFIG_SYS_NAND_ECCBYTES        3
  57#define CONFIG_SYS_NAND_PAGE_COUNT      (CONFIG_SYS_NAND_BLOCK_SIZE / \
  58                                                CONFIG_SYS_NAND_PAGE_SIZE)
  59#endif  /* CONFIG_NAND_LPC32XX_SLC */
  60
  61/* NOR Flash */
  62
  63/* USB OHCI */
  64#if defined(CONFIG_USB_OHCI_LPC32XX)
  65#define CONFIG_USB_OHCI_NEW
  66#define CONFIG_SYS_USB_OHCI_CPU_INIT
  67#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      1
  68#define CONFIG_SYS_USB_OHCI_REGS_BASE           USB_BASE
  69#define CONFIG_SYS_USB_OHCI_SLOT_NAME           "lpc32xx-ohci"
  70#endif
  71
  72#endif /* _LPC32XX_CONFIG_H */
  73