LXR uboot/arch/arm/include/asm/arch-rockchip/ddr

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
   4 */
   5
   6#ifndef __ASM_ARCH_DDR_RK3368_H__
   7#define __ASM_ARCH_DDR_RK3368_H__
   8
   9/*
  10 * The RK3368 DDR PCTL differs from the incarnation in the RK3288 only
  11 * in a few details. Most notably, it has an additional field to track
  12 * tREFI in controller cycles (i.e. trefi_mem_ddr3).
  13 */
  14struct rk3368_ddr_pctl {
  15        u32 scfg;
  16        u32 sctl;
  17        u32 stat;
  18        u32 intrstat;
  19        u32 reserved0[12];
  20        u32 mcmd;
  21        u32 powctl;
  22        u32 powstat;
  23        u32 cmdtstat;
  24        u32 cmdtstaten;
  25        u32 reserved1[3];
  26        u32 mrrcfg0;
  27        u32 mrrstat0;
  28        u32 mrrstat1;
  29        u32 reserved2[4];
  30        u32 mcfg1;
  31        u32 mcfg;
  32        u32 ppcfg;
  33        u32 mstat;
  34        u32 lpddr2zqcfg;
  35        u32 reserved3;
  36        u32 dtupdes;
  37        u32 dtuna;
  38        u32 dtune;
  39        u32 dtuprd0;
  40        u32 dtuprd1;
  41        u32 dtuprd2;
  42        u32 dtuprd3;
  43        u32 dtuawdt;
  44        u32 reserved4[3];
  45        u32 togcnt1u;
  46        u32 tinit;
  47        u32 trsth;
  48        u32 togcnt100n;
  49        u32 trefi;
  50        u32 tmrd;
  51        u32 trfc;
  52        u32 trp;
  53        u32 trtw;
  54        u32 tal;
  55        u32 tcl;
  56        u32 tcwl;
  57        u32 tras;
  58        u32 trc;
  59        u32 trcd;
  60        u32 trrd;
  61        u32 trtp;
  62        u32 twr;
  63        u32 twtr;
  64        u32 texsr;
  65        u32 txp;
  66        u32 txpdll;
  67        u32 tzqcs;
  68        u32 tzqcsi;
  69        u32 tdqs;
  70        u32 tcksre;
  71        u32 tcksrx;
  72        u32 tcke;
  73        u32 tmod;
  74        u32 trstl;
  75        u32 tzqcl;
  76        u32 tmrr;
  77        u32 tckesr;
  78        u32 tdpd;
  79        u32 trefi_mem_ddr3;
  80        u32 reserved5[45];
  81        u32 dtuwactl;
  82        u32 dturactl;
  83        u32 dtucfg;
  84        u32 dtuectl;
  85        u32 dtuwd0;
  86        u32 dtuwd1;
  87        u32 dtuwd2;
  88        u32 dtuwd3;
  89        u32 dtuwdm;
  90        u32 dturd0;
  91        u32 dturd1;
  92        u32 dturd2;
  93        u32 dturd3;
  94        u32 dtulfsrwd;
  95        u32 dtulfsrrd;
  96        u32 dtueaf;
  97        u32 dfitctrldelay;
  98        u32 dfiodtcfg;
  99        u32 dfiodtcfg1;
 100        u32 dfiodtrankmap;
 101        u32 dfitphywrdata;
 102        u32 dfitphywrlat;
 103        u32 reserved7[2];
 104        u32 dfitrddataen;
 105        u32 dfitphyrdlat;
 106        u32 reserved8[2];
 107        u32 dfitphyupdtype0;
 108        u32 dfitphyupdtype1;
 109        u32 dfitphyupdtype2;
 110        u32 dfitphyupdtype3;
 111        u32 dfitctrlupdmin;
 112        u32 dfitctrlupdmax;
 113        u32 dfitctrlupddly;
 114        u32 reserved9;
 115        u32 dfiupdcfg;
 116        u32 dfitrefmski;
 117        u32 dfitctrlupdi;
 118        u32 reserved10[4];
 119        u32 dfitrcfg0;
 120        u32 dfitrstat0;
 121        u32 dfitrwrlvlen;
 122        u32 dfitrrdlvlen;
 123        u32 dfitrrdlvlgateen;
 124        u32 dfiststat0;
 125        u32 dfistcfg0;
 126        u32 dfistcfg1;
 127        u32 reserved11;
 128        u32 dfitdramclken;
 129        u32 dfitdramclkdis;
 130        u32 dfistcfg2;
 131        u32 dfistparclr;
 132        u32 dfistparlog;
 133        u32 reserved12[3];
 134        u32 dfilpcfg0;
 135        u32 reserved13[3];
 136        u32 dfitrwrlvlresp0;
 137        u32 dfitrwrlvlresp1;
 138        u32 dfitrwrlvlresp2;
 139        u32 dfitrrdlvlresp0;
 140        u32 dfitrrdlvlresp1;
 141        u32 dfitrrdlvlresp2;
 142        u32 dfitrwrlvldelay0;
 143        u32 dfitrwrlvldelay1;
 144        u32 dfitrwrlvldelay2;
 145        u32 dfitrrdlvldelay0;
 146        u32 dfitrrdlvldelay1;
 147        u32 dfitrrdlvldelay2;
 148        u32 dfitrrdlvlgatedelay0;
 149        u32 dfitrrdlvlgatedelay1;
 150        u32 dfitrrdlvlgatedelay2;
 151        u32 dfitrcmd;
 152        u32 reserved14[46];
 153        u32 ipvr;
 154        u32 iptr;
 155};
 156check_member(rk3368_ddr_pctl, iptr, 0x03fc);
 157
 158struct rk3368_ddrphy {
 159        u32 reg[0x100];
 160};
 161check_member(rk3368_ddrphy, reg[0xff], 0x03fc);
 162
 163struct rk3368_msch {
 164        u32 coreid;
 165        u32 revisionid;
 166        u32 ddrconf;
 167        u32 ddrtiming;
 168        u32 ddrmode;
 169        u32 readlatency;
 170        u32 reserved1[8];
 171        u32 activate;
 172        u32 devtodev;
 173};
 174check_member(rk3368_msch, devtodev, 0x003c);
 175
 176/* GRF_SOC_CON0 */
 177enum {
 178        NOC_RSP_ERR_STALL = BIT(9),
 179        MOBILE_DDR_SEL = BIT(4),
 180        DDR0_16BIT_EN = BIT(3),
 181        MSCH0_MAINDDR3_DDR3 = BIT(2),
 182        MSCH0_MAINPARTIALPOP = BIT(1),
 183        UPCTL_C_ACTIVE = BIT(0),
 184};
 185
 186#endif
 187