1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * sun8i H3 platform dram controller register and constant defines 4 * 5 * (C) Copyright 2007-2015 Allwinner Technology Co. 6 * Jerry Wang <wangflord@allwinnertech.com> 7 * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> 8 * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com> 9 * (C) Copyright 2015 Jens Kuske <jenskuske@gmail.com> 10 */ 11 12#ifndef _SUNXI_DRAM_SUN8I_H3_H 13#define _SUNXI_DRAM_SUN8I_H3_H 14 15#include <linux/bitops.h> 16 17struct sunxi_mctl_com_reg { 18 u32 cr; /* 0x00 control register */ 19 u32 cr_r1; /* 0x04 rank 1 control register (R40 only) */ 20 u8 res0[0x4]; /* 0x08 */ 21 u32 tmr; /* 0x0c (unused on H3) */ 22 u32 mcr[16][2]; /* 0x10 */ 23 u32 bwcr; /* 0x90 bandwidth control register */ 24 u32 maer; /* 0x94 master enable register */ 25 u32 mapr; /* 0x98 master priority register */ 26 u32 mcgcr; /* 0x9c */ 27 u32 cpu_bwcr; /* 0xa0 */ 28 u32 gpu_bwcr; /* 0xa4 */ 29 u32 ve_bwcr; /* 0xa8 */ 30 u32 disp_bwcr; /* 0xac */ 31 u32 other_bwcr; /* 0xb0 */ 32 u32 total_bwcr; /* 0xb4 */ 33 u8 res1[0x8]; /* 0xb8 */ 34 u32 swonr; /* 0xc0 */ 35 u32 swoffr; /* 0xc4 */ 36 u8 res2[0x8]; /* 0xc8 */ 37 u32 cccr; /* 0xd0 */ 38 u8 res3[0x54]; /* 0xd4 */ 39 u32 mdfs_bwlr[3]; /* 0x128 (unused on H3) */ 40 u8 res4[0x6cc]; /* 0x134 */ 41 u32 protect; /* 0x800 */ 42}; 43 44#define MCTL_CR_BL8 (0x4 << 20) 45 46#define MCTL_CR_1T (0x1 << 19) 47#define MCTL_CR_2T (0x0 << 19) 48 49#define MCTL_CR_LPDDR3 (0x7 << 16) 50#define MCTL_CR_LPDDR2 (0x6 << 16) 51#define MCTL_CR_DDR3 (0x3 << 16) 52#define MCTL_CR_DDR2 (0x2 << 16) 53 54#define MCTL_CR_SEQUENTIAL (0x1 << 15) 55#define MCTL_CR_INTERLEAVED (0x0 << 15) 56 57#define MCTL_CR_FULL_WIDTH (0x1 << 12) 58#define MCTL_CR_HALF_WIDTH (0x0 << 12) 59#define MCTL_CR_BUS_FULL_WIDTH(x) ((x) << 12) 60 61#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8) 62#define MCTL_CR_ROW_BITS(x) (((x) - 1) << 4) 63#define MCTL_CR_EIGHT_BANKS (0x1 << 2) 64#define MCTL_CR_FOUR_BANKS (0x0 << 2) 65#define MCTL_CR_DUAL_RANK (0x1 << 0) 66#define MCTL_CR_SINGLE_RANK (0x0 << 0) 67 68/* 69 * CR_R1 is a register found in the R40's DRAM controller. It sets various 70 * parameters for rank 1. Bits [11:0] have the same meaning as the bits in 71 * MCTL_CR, but they apply to rank 1 only. This implies we can have 72 * different chips for rank 1 than rank 0. 73 * 74 * As address line A15 and CS1 chip select for rank 1 are muxed on the same 75 * pin, if single rank is used, A15 must be muxed in. 76 */ 77#define MCTL_CR_R1_MUX_A15 (0x1 << 21) 78 79#define PROTECT_MAGIC (0x94be6fa3) 80 81struct sunxi_mctl_ctl_reg { 82 u32 pir; /* 0x00 PHY initialization register */ 83 u32 pwrctl; /* 0x04 */ 84 u32 mrctrl; /* 0x08 */ 85 u32 clken; /* 0x0c */ 86 u32 pgsr[2]; /* 0x10 PHY general status registers */ 87 u32 statr; /* 0x18 */ 88 u8 res1[0x10]; /* 0x1c */ 89 u32 lp3mr11; /* 0x2c */ 90 u32 mr[4]; /* 0x30 mode registers */ 91 u32 pllgcr; /* 0x40 */ 92 u32 ptr[5]; /* 0x44 PHY timing registers */ 93 u32 dramtmg[9]; /* 0x58 DRAM timing registers */ 94 u32 odtcfg; /* 0x7c */ 95 u32 pitmg[2]; /* 0x80 PHY interface timing registers */ 96 u8 res2[0x4]; /* 0x88 */ 97 u32 rfshctl0; /* 0x8c */ 98 u32 rfshtmg; /* 0x90 refresh timing */ 99 u32 rfshctl1; /* 0x94 */ 100 u32 pwrtmg; /* 0x98 */ 101 u8 res3[0x1c]; /* 0x9c */ 102 u32 vtfcr; /* 0xb8 (unused on H3) */ 103 u32 dqsgmr; /* 0xbc */ 104 u32 dtcr; /* 0xc0 */ 105 u32 dtar[4]; /* 0xc4 */ 106 u32 dtdr[2]; /* 0xd4 */ 107 u32 dtmr[2]; /* 0xdc */ 108 u32 dtbmr; /* 0xe4 */ 109 u32 catr[2]; /* 0xe8 */ 110 u32 dtedr[2]; /* 0xf0 */ 111 u8 res4[0x8]; /* 0xf8 */ 112 u32 pgcr[4]; /* 0x100 PHY general configuration registers */ 113 u32 iovcr[2]; /* 0x110 */ 114 u32 dqsdr; /* 0x118 */ 115 u32 dxccr; /* 0x11c */ 116 u32 odtmap; /* 0x120 */ 117 u32 zqctl[2]; /* 0x124 */ 118 u8 res6[0x14]; /* 0x12c */ 119 u32 zqcr; /* 0x140 ZQ control register */ 120 u32 zqsr; /* 0x144 ZQ status register */ 121 u32 zqdr[3]; /* 0x148 ZQ data registers */ 122 u8 res7[0x6c]; /* 0x154 */ 123 u32 sched; /* 0x1c0 */ 124 u32 perfhpr[2]; /* 0x1c4 */ 125 u32 perflpr[2]; /* 0x1cc */ 126 u32 perfwr[2]; /* 0x1d4 */ 127 u8 res8[0x24]; /* 0x1dc */ 128 u32 acmdlr; /* 0x200 AC master delay line register */ 129 u32 aclcdlr; /* 0x204 AC local calibrated delay line register */ 130 u32 aciocr; /* 0x208 AC I/O configuration register */ 131 u8 res9[0x4]; /* 0x20c */ 132 u32 acbdlr[31]; /* 0x210 AC bit delay line registers */ 133 u8 res10[0x74]; /* 0x28c */ 134 struct { /* 0x300 DATX8 modules*/ 135 u32 mdlr; /* 0x00 master delay line register */ 136 u32 lcdlr[3]; /* 0x04 local calibrated delay line registers */ 137 u32 bdlr[11]; /* 0x10 bit delay line registers */ 138 u32 sdlr; /* 0x3c output enable bit delay registers */ 139 u32 gtr; /* 0x40 general timing register */ 140 u32 gcr; /* 0x44 general configuration register */ 141 u32 gsr[3]; /* 0x48 general status registers */ 142 u8 res0[0x2c]; /* 0x54 */ 143 } dx[4]; 144 u8 res11[0x388]; /* 0x500 */ 145 u32 upd2; /* 0x888 */ 146}; 147 148#define PTR3_TDINIT1(x) ((x) << 20) 149#define PTR3_TDINIT0(x) ((x) << 0) 150 151#define PTR4_TDINIT3(x) ((x) << 20) 152#define PTR4_TDINIT2(x) ((x) << 0) 153 154#define DRAMTMG0_TWTP(x) ((x) << 24) 155#define DRAMTMG0_TFAW(x) ((x) << 16) 156#define DRAMTMG0_TRAS_MAX(x) ((x) << 8) 157#define DRAMTMG0_TRAS(x) ((x) << 0) 158 159#define DRAMTMG1_TXP(x) ((x) << 16) 160#define DRAMTMG1_TRTP(x) ((x) << 8) 161#define DRAMTMG1_TRC(x) ((x) << 0) 162 163#define DRAMTMG2_TCWL(x) ((x) << 24) 164#define DRAMTMG2_TCL(x) ((x) << 16) 165#define DRAMTMG2_TRD2WR(x) ((x) << 8) 166#define DRAMTMG2_TWR2RD(x) ((x) << 0) 167 168#define DRAMTMG3_TMRW(x) ((x) << 16) 169#define DRAMTMG3_TMRD(x) ((x) << 12) 170#define DRAMTMG3_TMOD(x) ((x) << 0) 171 172#define DRAMTMG4_TRCD(x) ((x) << 24) 173#define DRAMTMG4_TCCD(x) ((x) << 16) 174#define DRAMTMG4_TRRD(x) ((x) << 8) 175#define DRAMTMG4_TRP(x) ((x) << 0) 176 177#define DRAMTMG5_TCKSRX(x) ((x) << 24) 178#define DRAMTMG5_TCKSRE(x) ((x) << 16) 179#define DRAMTMG5_TCKESR(x) ((x) << 8) 180#define DRAMTMG5_TCKE(x) ((x) << 0) 181 182#define RFSHTMG_TREFI(x) ((x) << 16) 183#define RFSHTMG_TRFC(x) ((x) << 0) 184 185#define PIR_CLRSR (0x1 << 27) /* clear status registers */ 186#define PIR_QSGATE (0x1 << 10) /* Read DQS gate training */ 187#define PIR_DRAMINIT (0x1 << 8) /* DRAM initialization */ 188#define PIR_DRAMRST (0x1 << 7) /* DRAM reset */ 189#define PIR_PHYRST (0x1 << 6) /* PHY reset */ 190#define PIR_DCAL (0x1 << 5) /* DDL calibration */ 191#define PIR_PLLINIT (0x1 << 4) /* PLL initialization */ 192#define PIR_ZCAL (0x1 << 1) /* ZQ calibration */ 193#define PIR_INIT (0x1 << 0) /* PHY initialization trigger */ 194 195#define PGSR_INIT_DONE (0x1 << 0) /* PHY init done */ 196 197#define ZQCR_PWRDOWN (1U << 31) /* ZQ power down */ 198 199#define ACBDLR_WRITE_DELAY(x) ((x) << 8) 200 201#define DXBDLR_DQ(x) (x) /* DQ0-7 BDLR index */ 202#define DXBDLR_DM 8 /* DM BDLR index */ 203#define DXBDLR_DQS 9 /* DQS BDLR index */ 204#define DXBDLR_DQSN 10 /* DQSN BDLR index */ 205 206#define DXBDLR_WRITE_DELAY(x) ((x) << 8) 207#define DXBDLR_READ_DELAY(x) ((x) << 0) 208 209/* 210 * The delay parameters below allow to allegedly specify delay times of some 211 * unknown unit for each individual bit trace in each of the four data bytes 212 * the 32-bit wide access consists of. Also three control signals can be 213 * adjusted individually. 214 */ 215#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE) 216/* The eight data lines (DQn) plus DM, DQS and DQSN */ 217#define LINES_PER_BYTE_LANE (BITS_PER_BYTE + 3) 218struct dram_para { 219 u16 page_size; 220 u8 bus_full_width; 221 u8 dual_rank; 222 u8 row_bits; 223 u8 bank_bits; 224 const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; 225 const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; 226 const u8 ac_delays[31]; 227}; 228 229static inline int ns_to_t(int nanoseconds) 230{ 231 const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2; 232 233 return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); 234} 235 236void mctl_set_timing_params(uint16_t socid, struct dram_para *para); 237 238#endif /* _SUNXI_DRAM_SUN8I_H3_H */ 239