uboot/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
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   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
   4 */
   5
   6#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
   7#define _SOCFPGA_S10_BASE_HARDWARE_H_
   8
   9#define SOCFPGA_CCU_ADDRESS                     0xf7000000
  10#define SOCFPGA_SDR_SCHEDULER_ADDRESS           0xf8000400
  11#define SOCFPGA_HMC_MMR_IO48_ADDRESS            0xf8010000
  12#define SOCFPGA_SDR_ADDRESS                     0xf8011000
  13#define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS          0xf8020100
  14#define SOCFPGA_SMMU_ADDRESS                    0xfa000000
  15#define SOCFPGA_MAILBOX_ADDRESS                 0xffa30000
  16#define SOCFPGA_UART0_ADDRESS                   0xffc02000
  17#define SOCFPGA_UART1_ADDRESS                   0xffc02100
  18#define SOCFPGA_SPTIMER0_ADDRESS                0xffc03000
  19#define SOCFPGA_SPTIMER1_ADDRESS                0xffc03100
  20#define SOCFPGA_SYSTIMER0_ADDRESS               0xffd00000
  21#define SOCFPGA_SYSTIMER1_ADDRESS               0xffd00100
  22#define SOCFPGA_L4WD0_ADDRESS                   0xffd00200
  23#define SOCFPGA_L4WD1_ADDRESS                   0xffd00300
  24#define SOCFPGA_L4WD2_ADDRESS                   0xffd00400
  25#define SOCFPGA_L4WD3_ADDRESS                   0xffd00500
  26#define SOCFPGA_GTIMER_SEC_ADDRESS              0xffd01000
  27#define SOCFPGA_GTIMER_NSEC_ADDRESS             0xffd02000
  28#define SOCFPGA_CLKMGR_ADDRESS                  0xffd10000
  29#define SOCFPGA_RSTMGR_ADDRESS                  0xffd11000
  30#define SOCFPGA_SYSMGR_ADDRESS                  0xffd12000
  31#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS     0xffd13000
  32#define SOCFPGA_FIREWALL_L4_PER                 0xffd21000
  33#define SOCFPGA_FIREWALL_L4_SYS                 0xffd21100
  34#define SOCFPGA_FIREWALL_SOC2FPGA               0xffd21200
  35#define SOCFPGA_FIREWALL_LWSOC2FPGA             0xffd21300
  36#define SOCFPGA_FIREWALL_TCU                    0xffd21400
  37#define SOCFPGA_DMANONSECURE_ADDRESS            0xffda0000
  38#define SOCFPGA_DMASECURE_ADDRESS               0xffda1000
  39#define SOCFPGA_OCRAM_ADDRESS                   0xffe00000
  40#define GICD_BASE                               0xfffc1000
  41#define GICC_BASE                               0xfffc2000
  42
  43#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */
  44