1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * MCF5227x Internal Memory Map 4 * 5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 */ 8 9#ifndef __IMMAP_5227X__ 10#define __IMMAP_5227X__ 11 12/* Module Base Addresses */ 13#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000) 14#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000) 15#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000) 16#define MMAP_CAN (CONFIG_SYS_MBAR + 0x00020000) 17#define MMAP_RTC (CONFIG_SYS_MBAR + 0x0003C000) 18#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040010) 19#define MMAP_SCM3 (CONFIG_SYS_MBAR + 0x00040070) 20#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000) 21#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000) 22#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x0004C000) 23#define MMAP_IACK (CONFIG_SYS_MBAR + 0x00054000) 24#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000) 25#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x0005C000) 26#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000) 27#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000) 28#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000) 29#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000) 30#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000) 31#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000) 32#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000) 33#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000) 34#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000) 35#define MMAP_PWM (CONFIG_SYS_MBAR + 0x00090000) 36#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00094000) 37#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000) 38#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004) 39#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000) 40#define MMAP_ADC (CONFIG_SYS_MBAR + 0x000A8000) 41#define MMAP_LCD (CONFIG_SYS_MBAR + 0x000AC000) 42#define MMAP_LCD_BGLUT (CONFIG_SYS_MBAR + 0x000AC800) 43#define MMAP_LCD_GWLUT (CONFIG_SYS_MBAR + 0x000ACC00) 44#define MMAP_USBHW (CONFIG_SYS_MBAR + 0x000B0000) 45#define MMAP_USBCAPS (CONFIG_SYS_MBAR + 0x000B0100) 46#define MMAP_USBEHCI (CONFIG_SYS_MBAR + 0x000B0140) 47#define MMAP_USBOTG (CONFIG_SYS_MBAR + 0x000B01A0) 48#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000B8000) 49#define MMAP_SSI (CONFIG_SYS_MBAR + 0x000BC000) 50#define MMAP_PLL (CONFIG_SYS_MBAR + 0x000C0000) 51 52#include <asm/coldfire/crossbar.h> 53#include <asm/coldfire/dspi.h> 54#include <asm/coldfire/edma.h> 55#include <asm/coldfire/eport.h> 56#include <asm/coldfire/flexbus.h> 57#include <asm/coldfire/flexcan.h> 58#include <asm/coldfire/intctrl.h> 59#include <asm/coldfire/lcd.h> 60#include <asm/coldfire/pwm.h> 61#include <asm/coldfire/ssi.h> 62 63/* Reset Controller Module (RCM) */ 64typedef struct rcm { 65 u8 rcr; 66 u8 rsr; 67} rcm_t; 68 69/* Chip Configuration Module (CCM) */ 70typedef struct ccm { 71 u16 ccr; /* Chip Configuration (Rd-only) */ 72 u16 resv1; 73 u16 rcon; /* Reset Configuration (Rd-only) */ 74 u16 cir; /* Chip Identification (Rd-only) */ 75 u32 resv2; 76 u16 misccr; /* Miscellaneous Control */ 77 u16 cdr; /* Clock Divider */ 78 u16 uocsr; /* USB On-the-Go Controller Status */ 79 u16 resv4; 80 u16 sbfsr; /* Serial Boot Status */ 81 u16 sbfcr; /* Serial Boot Control */ 82} ccm_t; 83 84typedef struct canex_ctrl { 85 can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */ 86 u32 res0[0x700]; /* 0x100 */ 87 can_msg_t rxim[16]; /* 0x800 Rx Individual Mask 0-15 */ 88} canex_t; 89 90/* General Purpose I/O Module (GPIO) */ 91typedef struct gpio { 92 /* Port Output Data Registers */ 93 u8 podr_be; /* 0x00 */ 94 u8 podr_cs; /* 0x01 */ 95 u8 podr_fbctl; /* 0x02 */ 96 u8 podr_i2c; /* 0x03 */ 97 u8 rsvd1; /* 0x04 */ 98 u8 podr_uart; /* 0x05 */ 99 u8 podr_dspi; /* 0x06 */ 100 u8 podr_timer; /* 0x07 */ 101 u8 podr_lcdctl; /* 0x08 */ 102 u8 podr_lcddatah; /* 0x09 */ 103 u8 podr_lcddatam; /* 0x0A */ 104 u8 podr_lcddatal; /* 0x0B */ 105 106 /* Port Data Direction Registers */ 107 u8 pddr_be; /* 0x0C */ 108 u8 pddr_cs; /* 0x0D */ 109 u8 pddr_fbctl; /* 0x0E */ 110 u8 pddr_i2c; /* 0x0F */ 111 u8 rsvd2; /* 0x10 */ 112 u8 pddr_uart; /* 0x11 */ 113 u8 pddr_dspi; /* 0x12 */ 114 u8 pddr_timer; /* 0x13 */ 115 u8 pddr_lcdctl; /* 0x14 */ 116 u8 pddr_lcddatah; /* 0x15 */ 117 u8 pddr_lcddatam; /* 0x16 */ 118 u8 pddr_lcddatal; /* 0x17 */ 119 120 /* Port Pin Data/Set Data Registers */ 121 u8 ppdsdr_be; /* 0x18 */ 122 u8 ppdsdr_cs; /* 0x19 */ 123 u8 ppdsdr_fbctl; /* 0x1A */ 124 u8 ppdsdr_i2c; /* 0x1B */ 125 u8 rsvd3; /* 0x1C */ 126 u8 ppdsdr_uart; /* 0x1D */ 127 u8 ppdsdr_dspi; /* 0x1E */ 128 u8 ppdsdr_timer; /* 0x1F */ 129 u8 ppdsdr_lcdctl; /* 0x20 */ 130 u8 ppdsdr_lcddatah; /* 0x21 */ 131 u8 ppdsdr_lcddatam; /* 0x22 */ 132 u8 ppdsdr_lcddatal; /* 0x23 */ 133 134 /* Port Clear Output Data Registers */ 135 u8 pclrr_be; /* 0x24 */ 136 u8 pclrr_cs; /* 0x25 */ 137 u8 pclrr_fbctl; /* 0x26 */ 138 u8 pclrr_i2c; /* 0x27 */ 139 u8 rsvd4; /* 0x28 */ 140 u8 pclrr_uart; /* 0x29 */ 141 u8 pclrr_dspi; /* 0x2A */ 142 u8 pclrr_timer; /* 0x2B */ 143 u8 pclrr_lcdctl; /* 0x2C */ 144 u8 pclrr_lcddatah; /* 0x2D */ 145 u8 pclrr_lcddatam; /* 0x2E */ 146 u8 pclrr_lcddatal; /* 0x2F */ 147 148 /* Pin Assignment Registers */ 149 u8 par_be; /* 0x30 */ 150 u8 par_cs; /* 0x31 */ 151 u8 par_fbctl; /* 0x32 */ 152 u8 par_i2c; /* 0x33 */ 153 u16 par_uart; /* 0x34 */ 154 u8 par_dspi; /* 0x36 */ 155 u8 par_timer; /* 0x37 */ 156 u8 par_lcdctl; /* 0x38 */ 157 u8 par_irq; /* 0x39 */ 158 u16 rsvd6; /* 0x3A - 0x3B */ 159 u32 par_lcdh; /* 0x3C */ 160 u32 par_lcdl; /* 0x40 */ 161 162 /* Mode select control registers */ 163 u8 mscr_fb; /* 0x44 */ 164 u8 mscr_sdram; /* 0x45 */ 165 166 u16 rsvd7; /* 0x46 - 0x47 */ 167 u8 dscr_dspi; /* 0x48 */ 168 u8 dscr_timer; /* 0x49 */ 169 u8 dscr_i2c; /* 0x4A */ 170 u8 dscr_lcd; /* 0x4B */ 171 u8 dscr_debug; /* 0x4C */ 172 u8 dscr_clkrst; /* 0x4D */ 173 u8 dscr_irq; /* 0x4E */ 174 u8 dscr_uart; /* 0x4F */ 175} gpio_t; 176 177/* SDRAM Controller (SDRAMC) */ 178typedef struct sdramc { 179 u32 sdmr; /* Mode/Extended Mode */ 180 u32 sdcr; /* Control */ 181 u32 sdcfg1; /* Configuration 1 */ 182 u32 sdcfg2; /* Chip Select */ 183 u8 resv0[0x100]; 184 u32 sdcs0; /* Mode/Extended Mode */ 185 u32 sdcs1; /* Mode/Extended Mode */ 186} sdramc_t; 187 188/* Phase Locked Loop (PLL) */ 189typedef struct pll { 190 u32 pcr; /* PLL Control */ 191 u32 psr; /* PLL Status */ 192} pll_t; 193 194/* System Control Module register */ 195typedef struct scm1 { 196 u32 mpr; /* 0x00 Master Privilege */ 197 u32 rsvd1[7]; 198 u32 pacra; /* 0x20 */ 199 u32 pacrb; /* 0x24 */ 200 u32 pacrc; /* 0x28 */ 201 u32 pacrd; /* 0x2C */ 202 u32 rsvd2[4]; 203 u32 pacre; /* 0x40 */ 204 u32 pacrf; /* 0x44 */ 205 u32 pacrg; /* 0x48 */ 206 u32 rsvd3; 207 u32 pacri; /* 0x50 */ 208} scm1_t; 209 210typedef struct scm2_ctrl { 211 u8 res1[3]; /* 0x00 - 0x02 */ 212 u8 wcr; /* 0x03 wakeup control */ 213 u16 res2; /* 0x04 - 0x05 */ 214 u16 cwcr; /* 0x06 Core Watchdog Control */ 215 u8 res3[3]; /* 0x08 - 0x0A */ 216 u8 cwsr; /* 0x0B Core Watchdog Service */ 217 u8 res4[2]; /* 0x0C - 0x0D */ 218 u8 scmisr; /* 0x0F Interrupt Status */ 219 u32 res5; /* 0x20 */ 220 u32 bcr; /* 0x24 Burst Configuration */ 221} scm2_t; 222 223typedef struct scm3_ctrl { 224 u32 cfadr; /* 0x00 Core Fault Address */ 225 u8 res7; /* 0x04 */ 226 u8 cfier; /* 0x05 Core Fault Interrupt Enable */ 227 u8 cfloc; /* 0x06 Core Fault Location */ 228 u8 cfatr; /* 0x07 Core Fault Attributes */ 229 u32 cfdtr; /* 0x08 Core Fault Data */ 230} scm3_t; 231 232typedef struct rtcex { 233 u32 rsvd1[3]; 234 u32 gocu; 235 u32 gocl; 236} rtcex_t; 237#endif /* __IMMAP_5227X__ */ 238