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6#ifndef _MSCC_JR2_ICPU_CFG_H_
7#define _MSCC_JR2_ICPU_CFG_H_
8
9#define ICPU_GPR(x) (0x4 * (x))
10#define ICPU_GPR_RSZ 0x4
11
12#define ICPU_RESET 0x20
13
14#define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3)
15#define ICPU_RESET_CORE_RST_PROTECT BIT(2)
16#define ICPU_RESET_CORE_RST_FORCE BIT(1)
17#define ICPU_RESET_MEM_RST_FORCE BIT(0)
18
19#define ICPU_GENERAL_CTRL 0x24
20
21#define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(15)
22#define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(14)
23#define ICPU_GENERAL_CTRL_CPU_8051_IROM_ENA BIT(13)
24#define ICPU_GENERAL_CTRL_CPU_MIPS_DIS BIT(12)
25#define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ENA BIT(11)
26#define ICPU_GENERAL_CTRL_IF_PI_SLV_DONEPOL BIT(10)
27#define ICPU_GENERAL_CTRL_IF_PI_MST_ENA BIT(9)
28#define ICPU_GENERAL_CTRL_IF_PI_SLV_ENA BIT(8)
29#define ICPU_GENERAL_CTRL_IF_SI_OWNER(x) (((x) << 6) & GENMASK(7, 6))
30#define ICPU_GENERAL_CTRL_IF_SI_OWNER_M GENMASK(7, 6)
31#define ICPU_GENERAL_CTRL_IF_SI_OWNER_X(x) (((x) & GENMASK(7, 6)) >> 4)
32#define ICPU_GENERAL_CTRL_IF_SI1_OWNER(x) (((x) << 4) & GENMASK(5, 4))
33#define ICPU_GENERAL_CTRL_IF_SI1_OWNER_M GENMASK(5, 4)
34#define ICPU_GENERAL_CTRL_IF_SI1_OWNER_X(x) (((x) & GENMASK(5, 4)) >> 4)
35#define ICPU_GENERAL_CTRL_SSI_MST_CONTENTION BIT(3)
36#define ICPU_GENERAL_CTRL_CPU_BE_ENA BIT(2)
37#define ICPU_GENERAL_CTRL_CPU_DIS BIT(1)
38#define ICPU_GENERAL_CTRL_BOOT_MODE_ENA BIT(0)
39
40#define ICPU_SPI_MST_CFG 0x3c
41
42#define ICPU_SPI_MST_CFG_A32B_ENA BIT(11)
43#define ICPU_SPI_MST_CFG_FAST_READ_ENA BIT(10)
44#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5))
45#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_M GENMASK(9, 5)
46#define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5)
47#define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0))
48#define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0)
49
50#define ICPU_SW_MODE 0x50
51
52#define ICPU_SW_MODE_SW_PIN_CTRL_MODE BIT(13)
53#define ICPU_SW_MODE_SW_SPI_SCK BIT(12)
54#define ICPU_SW_MODE_SW_SPI_SCK_OE BIT(11)
55#define ICPU_SW_MODE_SW_SPI_SDO BIT(10)
56#define ICPU_SW_MODE_SW_SPI_SDO_OE BIT(9)
57#define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5))
58#define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5)
59#define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5)
60#define ICPU_SW_MODE_SW_SPI_CS_OE(x) (((x) << 1) & GENMASK(4, 1))
61#define ICPU_SW_MODE_SW_SPI_CS_OE_M GENMASK(4, 1)
62#define ICPU_SW_MODE_SW_SPI_CS_OE_X(x) (((x) & GENMASK(4, 1)) >> 1)
63#define ICPU_SW_MODE_SW_SPI_SDI BIT(0)
64
65#define ICPU_INTR_ENA 0x88
66
67#define ICPU_DST_INTR_MAP(x) (0x98 + 0x4 * (x))
68#define ICPU_DST_INTR_MAP_RSZ 0x4
69
70#define ICPU_TIMER_TICK_DIV 0x108
71
72#define ICPU_TIMER_VALUE(x) (0x10c + 0x4 * (x))
73#define ICPU_TIMER_VALUE_RSZ 0x4
74
75#define ICPU_TIMER_CTRL(x) (0x124 + 0x4 * (x))
76#define ICPU_TIMER_CTRL_RSZ 0x4
77
78#define ICPU_TIMER_CTRL_MAX_FREQ_ENA BIT(3)
79#define ICPU_TIMER_CTRL_ONE_SHOT_ENA BIT(2)
80#define ICPU_TIMER_CTRL_TIMER_ENA BIT(1)
81#define ICPU_TIMER_CTRL_FORCE_RELOAD BIT(0)
82
83#define ICPU_MEMCTRL_CTRL 0x130
84
85#define ICPU_MEMCTRL_CTRL_PWR_DOWN BIT(3)
86#define ICPU_MEMCTRL_CTRL_MDSET BIT(2)
87#define ICPU_MEMCTRL_CTRL_STALL_REF_ENA BIT(1)
88#define ICPU_MEMCTRL_CTRL_INITIALIZE BIT(0)
89
90#define ICPU_MEMCTRL_CFG 0x134
91
92#define ICPU_MEMCTRL_CFG_DDR_512MBYTE_PLUS BIT(16)
93#define ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA BIT(15)
94#define ICPU_MEMCTRL_CFG_DDR_ECC_COR_ENA BIT(14)
95#define ICPU_MEMCTRL_CFG_DDR_ECC_ENA BIT(13)
96#define ICPU_MEMCTRL_CFG_DDR_WIDTH BIT(12)
97#define ICPU_MEMCTRL_CFG_DDR_MODE BIT(11)
98#define ICPU_MEMCTRL_CFG_BURST_SIZE BIT(10)
99#define ICPU_MEMCTRL_CFG_BURST_LEN BIT(9)
100#define ICPU_MEMCTRL_CFG_BANK_CNT BIT(8)
101#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR(x) (((x) << 4) & GENMASK(7, 4))
102#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_M GENMASK(7, 4)
103#define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_X(x) (((x) & GENMASK(7, 4)) >> 4)
104#define ICPU_MEMCTRL_CFG_MSB_COL_ADDR(x) ((x) & GENMASK(3, 0))
105#define ICPU_MEMCTRL_CFG_MSB_COL_ADDR_M GENMASK(3, 0)
106
107#define ICPU_MEMCTRL_STAT 0x138
108
109#define ICPU_MEMCTRL_STAT_RDATA_MASKED BIT(5)
110#define ICPU_MEMCTRL_STAT_RDATA_DUMMY BIT(4)
111#define ICPU_MEMCTRL_STAT_RDATA_ECC_ERR BIT(3)
112#define ICPU_MEMCTRL_STAT_RDATA_ECC_COR BIT(2)
113#define ICPU_MEMCTRL_STAT_PWR_DOWN_ACK BIT(1)
114#define ICPU_MEMCTRL_STAT_INIT_DONE BIT(0)
115
116#define ICPU_MEMCTRL_REF_PERIOD 0x13c
117
118#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(x) (((x) << 16) & GENMASK(19, 16))
119#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_M GENMASK(19, 16)
120#define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_X(x) (((x) & GENMASK(19, 16)) >> 16)
121#define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(x) ((x) & GENMASK(15, 0))
122#define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD_M GENMASK(15, 0)
123
124#define ICPU_MEMCTRL_ZQCAL 0x140
125
126#define ICPU_MEMCTRL_ZQCAL_ZQCAL_LONG BIT(1)
127#define ICPU_MEMCTRL_ZQCAL_ZQCAL_SHORT BIT(0)
128
129#define ICPU_MEMCTRL_TIMING0 0x144
130
131#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(x) (((x) << 28) & GENMASK(31, 28))
132#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_M GENMASK(31, 28)
133#define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28)
134#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY(x) (((x) << 24) & GENMASK(27, 24))
135#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_M GENMASK(27, 24)
136#define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24)
137#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY(x) (((x) << 20) & GENMASK(23, 20))
138#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_M GENMASK(23, 20)
139#define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_X(x) (((x) & GENMASK(23, 20)) >> 20)
140#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY(x) (((x) << 16) & GENMASK(19, 16))
141#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_M GENMASK(19, 16)
142#define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16)
143#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(x) (((x) << 12) & GENMASK(15, 12))
144#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_M GENMASK(15, 12)
145#define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
146#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY(x) (((x) << 8) & GENMASK(11, 8))
147#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_M GENMASK(11, 8)
148#define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
149#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY(x) (((x) << 4) & GENMASK(7, 4))
150#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_M GENMASK(7, 4)
151#define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
152#define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(x) ((x) & GENMASK(3, 0))
153#define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY_M GENMASK(3, 0)
154
155#define ICPU_MEMCTRL_TIMING1 0x148
156
157#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY(x) (((x) << 24) & GENMASK(31, 24))
158#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_M GENMASK(31, 24)
159#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_X(x) (((x) & GENMASK(31, 24)) >> 24)
160#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY(x) (((x) << 16) & GENMASK(23, 16))
161#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_M GENMASK(23, 16)
162#define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16)
163#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY(x) (((x) << 12) & GENMASK(15, 12))
164#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_M GENMASK(15, 12)
165#define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
166#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(x) (((x) << 8) & GENMASK(11, 8))
167#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_M GENMASK(11, 8)
168#define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
169#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY(x) (((x) << 4) & GENMASK(7, 4))
170#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_M GENMASK(7, 4)
171#define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
172#define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(x) ((x) & GENMASK(3, 0))
173#define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY_M GENMASK(3, 0)
174
175#define ICPU_MEMCTRL_TIMING2 0x14c
176
177#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY(x) (((x) << 28) & GENMASK(31, 28))
178#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_M GENMASK(31, 28)
179#define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28)
180#define ICPU_MEMCTRL_TIMING2_MDSET_DLY(x) (((x) << 24) & GENMASK(27, 24))
181#define ICPU_MEMCTRL_TIMING2_MDSET_DLY_M GENMASK(27, 24)
182#define ICPU_MEMCTRL_TIMING2_MDSET_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24)
183#define ICPU_MEMCTRL_TIMING2_REF_DLY(x) (((x) << 16) & GENMASK(23, 16))
184#define ICPU_MEMCTRL_TIMING2_REF_DLY_M GENMASK(23, 16)
185#define ICPU_MEMCTRL_TIMING2_REF_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16)
186#define ICPU_MEMCTRL_TIMING2_INIT_DLY(x) ((x) & GENMASK(15, 0))
187#define ICPU_MEMCTRL_TIMING2_INIT_DLY_M GENMASK(15, 0)
188
189#define ICPU_MEMCTRL_TIMING3 0x150
190
191#define ICPU_MEMCTRL_TIMING3_RMW_DLY(x) (((x) << 16) & GENMASK(19, 16))
192#define ICPU_MEMCTRL_TIMING3_RMW_DLY_M GENMASK(19, 16)
193#define ICPU_MEMCTRL_TIMING3_RMW_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16)
194#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY(x) (((x) << 12) & GENMASK(15, 12))
195#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_M GENMASK(15, 12)
196#define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12)
197#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY(x) (((x) << 8) & GENMASK(11, 8))
198#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_M GENMASK(11, 8)
199#define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8)
200#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(x) (((x) << 4) & GENMASK(7, 4))
201#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_M GENMASK(7, 4)
202#define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4)
203#define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(x) ((x) & GENMASK(3, 0))
204#define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY_M GENMASK(3, 0)
205
206#define ICPU_MEMCTRL_TIMING4 0x154
207
208#define ICPU_MEMCTRL_TIMING4_ZQCAL_INIT_DLY(x) (((x) << 20) & GENMASK(31, 20))
209#define ICPU_MEMCTRL_TIMING4_ZQCAL_INIT_DLY_M GENMASK(31, 20)
210#define ICPU_MEMCTRL_TIMING4_ZQCAL_INIT_DLY_X(x) (((x) & GENMASK(31, 20)) >> 20)
211#define ICPU_MEMCTRL_TIMING4_ZQCAL_LONG_DLY(x) (((x) << 8) & GENMASK(19, 8))
212#define ICPU_MEMCTRL_TIMING4_ZQCAL_LONG_DLY_M GENMASK(19, 8)
213#define ICPU_MEMCTRL_TIMING4_ZQCAL_LONG_DLY_X(x) (((x) & GENMASK(19, 8)) >> 8)
214#define ICPU_MEMCTRL_TIMING4_ZQCAL_SHORT_DLY(x) ((x) & GENMASK(7, 0))
215#define ICPU_MEMCTRL_TIMING4_ZQCAL_SHORT_DLY_M GENMASK(7, 0)
216
217#define ICPU_MEMCTRL_MR0_VAL 0x158
218
219#define ICPU_MEMCTRL_MR1_VAL 0x15c
220
221#define ICPU_MEMCTRL_MR2_VAL 0x160
222
223#define ICPU_MEMCTRL_MR3_VAL 0x164
224
225#define ICPU_MEMCTRL_TERMRES_CTRL 0x168
226
227#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_EXT BIT(11)
228#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA(x) (((x) << 7) & GENMASK(10, 7))
229#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_M GENMASK(10, 7)
230#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_X(x) (((x) & GENMASK(10, 7)) >> 7)
231#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_EXT BIT(6)
232#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA(x) (((x) << 2) & GENMASK(5, 2))
233#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_M GENMASK(5, 2)
234#define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_X(x) (((x) & GENMASK(5, 2)) >> 2)
235#define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_EXT BIT(1)
236#define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_ENA BIT(0)
237
238#define ICPU_MEMCTRL_DFT 0x16c
239
240#define ICPU_MEMCTRL_DFT_DDRDFT_LBW BIT(7)
241#define ICPU_MEMCTRL_DFT_DDRDFT_GATE_ENA BIT(6)
242#define ICPU_MEMCTRL_DFT_DDRDFT_TERM_ENA BIT(5)
243#define ICPU_MEMCTRL_DFT_DDRDFT_A10 BIT(4)
244#define ICPU_MEMCTRL_DFT_DDRDFT_STAT BIT(3)
245#define ICPU_MEMCTRL_DFT_DDRDFT_MODE(x) (((x) << 1) & GENMASK(2, 1))
246#define ICPU_MEMCTRL_DFT_DDRDFT_MODE_M GENMASK(2, 1)
247#define ICPU_MEMCTRL_DFT_DDRDFT_MODE_X(x) (((x) & GENMASK(2, 1)) >> 1)
248#define ICPU_MEMCTRL_DFT_DDRDFT_ENA BIT(0)
249
250#define ICPU_MEMCTRL_DQS_DLY(x) (0x170 + 0x4 * (x))
251#define ICPU_MEMCTRL_DQS_DLY_RSZ 0x4
252
253#define ICPU_MEMCTRL_DQS_DLY_TRAIN_DQ_ENA BIT(11)
254#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1(x) (((x) << 8) & GENMASK(10, 8))
255#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_M GENMASK(10, 8)
256#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_X(x) (((x) & GENMASK(10, 8)) >> 8)
257#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0(x) (((x) << 5) & GENMASK(7, 5))
258#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_M GENMASK(7, 5)
259#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_X(x) (((x) & GENMASK(7, 5)) >> 5)
260#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY(x) ((x) & GENMASK(4, 0))
261#define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_M GENMASK(4, 0)
262
263#define ICPU_MEMCTRL_DQS_AUTO (0x178 + 0x4 * (x))
264#define ICPU_MEMCTRL_DQS_AUTO_RSZ 0x4
265
266#define ICPU_MEMCTRL_DQS_AUTO_DQS_DRIFT(x) (((x) << 6) & GENMASK(7, 6))
267#define ICPU_MEMCTRL_DQS_AUTO_DQS_DRIFT_M GENMASK(7, 6)
268#define ICPU_MEMCTRL_DQS_AUTO_DQS_DRIFT_X(x) (((x) & GENMASK(7, 6)) >> 6)
269#define ICPU_MEMCTRL_DQS_AUTO_DQS_OVERFLOW BIT(5)
270#define ICPU_MEMCTRL_DQS_AUTO_DQS_UNDERFLOW BIT(4)
271#define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_SRC BIT(3)
272#define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_UP BIT(2)
273#define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_DOWN BIT(1)
274#define ICPU_MEMCTRL_DQS_AUTO_DQS_AUTO_ENA BIT(0)
275
276#define ICPU_MEMPHY_CFG 0x180
277
278#define ICPU_MEMPHY_CFG_PHY_FLUSH_DIS BIT(10)
279#define ICPU_MEMPHY_CFG_PHY_RD_ADJ_DIS BIT(9)
280#define ICPU_MEMPHY_CFG_PHY_DQS_EXT BIT(8)
281#define ICPU_MEMPHY_CFG_PHY_FIFO_RST BIT(7)
282#define ICPU_MEMPHY_CFG_PHY_DLL_BL_RST BIT(6)
283#define ICPU_MEMPHY_CFG_PHY_DLL_CL_RST BIT(5)
284#define ICPU_MEMPHY_CFG_PHY_ODT_OE BIT(4)
285#define ICPU_MEMPHY_CFG_PHY_CK_OE BIT(3)
286#define ICPU_MEMPHY_CFG_PHY_CL_OE BIT(2)
287#define ICPU_MEMPHY_CFG_PHY_SSTL_ENA BIT(1)
288#define ICPU_MEMPHY_CFG_PHY_RST BIT(0)
289
290#define ICPU_MEMPHY_ZCAL 0x1a8
291
292#define ICPU_MEMPHY_ZCAL_ZCAL_CLK_SEL BIT(9)
293#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT(x) (((x) << 5) & GENMASK(8, 5))
294#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_M GENMASK(8, 5)
295#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_X(x) (((x) & GENMASK(8, 5)) >> 5)
296#define ICPU_MEMPHY_ZCAL_ZCAL_PROG(x) (((x) << 1) & GENMASK(4, 1))
297#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_M GENMASK(4, 1)
298#define ICPU_MEMPHY_ZCAL_ZCAL_PROG_X(x) (((x) & GENMASK(4, 1)) >> 1)
299#define ICPU_MEMPHY_ZCAL_ZCAL_ENA BIT(0)
300
301#define ICPU_MEMPHY_ZCAL_STAT 0x1ac
302
303#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL(x) (((x) << 12) & GENMASK(31, 12))
304#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL_M GENMASK(31, 12)
305#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ZCTRL_X(x) (((x) & GENMASK(31, 12)) >> 12)
306#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU(x) (((x) << 8) & GENMASK(9, 8))
307#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU_M GENMASK(9, 8)
308#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPU_X(x) (((x) & GENMASK(9, 8)) >> 8)
309#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD(x) (((x) << 6) & GENMASK(7, 6))
310#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD_M GENMASK(7, 6)
311#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_ODTPD_X(x) (((x) & GENMASK(7, 6)) >> 6)
312#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU(x) (((x) << 4) & GENMASK(5, 4))
313#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU_M GENMASK(5, 4)
314#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PU_X(x) (((x) & GENMASK(5, 4)) >> 4)
315#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD(x) (((x) << 2) & GENMASK(3, 2))
316#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD_M GENMASK(3, 2)
317#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_STAT_PD_X(x) (((x) & GENMASK(3, 2)) >> 2)
318#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_ERR BIT(1)
319#define ICPU_MEMPHY_ZCAL_STAT_ZCAL_DONE BIT(0)
320
321#endif
322
