1menu "RISC-V architecture"
2 depends on RISCV
3
4config SYS_ARCH
5 default "riscv"
6
7choice
8 prompt "Target select"
9 optional
10
11config TARGET_AX25_AE350
12 bool "Support ax25-ae350"
13
14config TARGET_MICROCHIP_ICICLE
15 bool "Support Microchip PolarFire-SoC Icicle Board"
16
17config TARGET_QEMU_VIRT
18 bool "Support QEMU Virt Board"
19
20config TARGET_SIFIVE_FU540
21 bool "Support SiFive FU540 Board"
22
23endchoice
24
25config SYS_ICACHE_OFF
26 bool "Do not enable icache"
27 default n
28 help
29 Do not enable instruction cache in U-Boot.
30
31config SPL_SYS_ICACHE_OFF
32 bool "Do not enable icache in SPL"
33 depends on SPL
34 default SYS_ICACHE_OFF
35 help
36 Do not enable instruction cache in SPL.
37
38config SYS_DCACHE_OFF
39 bool "Do not enable dcache"
40 default n
41 help
42 Do not enable data cache in U-Boot.
43
44config SPL_SYS_DCACHE_OFF
45 bool "Do not enable dcache in SPL"
46 depends on SPL
47 default SYS_DCACHE_OFF
48 help
49 Do not enable data cache in SPL.
50
51
52source "board/AndesTech/ax25-ae350/Kconfig"
53source "board/emulation/qemu-riscv/Kconfig"
54source "board/microchip/mpfs_icicle/Kconfig"
55source "board/sifive/fu540/Kconfig"
56
57
58source "arch/riscv/cpu/ax25/Kconfig"
59source "arch/riscv/cpu/generic/Kconfig"
60
61
62
63choice
64 prompt "Base ISA"
65 default ARCH_RV32I
66
67config ARCH_RV32I
68 bool "RV32I"
69 select 32BIT
70 help
71 Choose this option to target the RV32I base integer instruction set.
72
73config ARCH_RV64I
74 bool "RV64I"
75 select 64BIT
76 select PHYS_64BIT
77 help
78 Choose this option to target the RV64I base integer instruction set.
79
80endchoice
81
82choice
83 prompt "Code Model"
84 default CMODEL_MEDLOW
85
86config CMODEL_MEDLOW
87 bool "medium low code model"
88 help
89 U-Boot and its statically defined symbols must lie within a single 2 GiB
90 address range and must lie between absolute addresses -2 GiB and +2 GiB.
91
92config CMODEL_MEDANY
93 bool "medium any code model"
94 help
95 U-Boot and its statically defined symbols must be within any single 2 GiB
96 address range.
97
98endchoice
99
100choice
101 prompt "Run Mode"
102 default RISCV_MMODE
103
104config RISCV_MMODE
105 bool "Machine"
106 help
107 Choose this option to build U-Boot for RISC-V M-Mode.
108
109config RISCV_SMODE
110 bool "Supervisor"
111 help
112 Choose this option to build U-Boot for RISC-V S-Mode.
113
114endchoice
115
116choice
117 prompt "SPL Run Mode"
118 default SPL_RISCV_MMODE
119 depends on SPL
120
121config SPL_RISCV_MMODE
122 bool "Machine"
123 help
124 Choose this option to build U-Boot SPL for RISC-V M-Mode.
125
126config SPL_RISCV_SMODE
127 bool "Supervisor"
128 help
129 Choose this option to build U-Boot SPL for RISC-V S-Mode.
130
131endchoice
132
133config RISCV_ISA_C
134 bool "Emit compressed instructions"
135 default y
136 help
137 Adds "C" to the ISA subsets that the toolchain is allowed to emit
138 when building U-Boot, which results in compressed instructions in the
139 U-Boot binary.
140
141config RISCV_ISA_A
142 def_bool y
143
144config 32BIT
145 bool
146
147config 64BIT
148 bool
149
150config SIFIVE_CLINT
151 bool
152 depends on RISCV_MMODE || SPL_RISCV_MMODE
153 select REGMAP
154 select SYSCON
155 select SPL_REGMAP if SPL
156 select SPL_SYSCON if SPL
157 help
158 The SiFive CLINT block holds memory-mapped control and status registers
159 associated with software and timer interrupts.
160
161config ANDES_PLIC
162 bool
163 depends on RISCV_MMODE || SPL_RISCV_MMODE
164 select REGMAP
165 select SYSCON
166 select SPL_REGMAP if SPL
167 select SPL_SYSCON if SPL
168 help
169 The Andes PLIC block holds memory-mapped claim and pending registers
170 associated with software interrupt.
171
172config ANDES_PLMT
173 bool
174 depends on RISCV_MMODE || SPL_RISCV_MMODE
175 select REGMAP
176 select SYSCON
177 select SPL_REGMAP if SPL
178 select SPL_SYSCON if SPL
179 help
180 The Andes PLMT block holds memory-mapped mtime register
181 associated with timer tick.
182
183config RISCV_RDTIME
184 bool
185 default y if RISCV_SMODE || SPL_RISCV_SMODE
186 help
187 The provides the riscv_get_time() API that is implemented using the
188 standard rdtime instruction. This is the case for S-mode U-Boot, and
189 is useful for processors that support rdtime in M-mode too.
190
191config SYS_MALLOC_F_LEN
192 default 0x1000
193
194config SMP
195 bool "Symmetric Multi-Processing"
196 help
197 This enables support for systems with more than one CPU. If
198 you say N here, U-Boot will run on single and multiprocessor
199 machines, but will use only one CPU of a multiprocessor
200 machine. If you say Y here, U-Boot will run on many, but not
201 all, single processor machines.
202
203config NR_CPUS
204 int "Maximum number of CPUs (2-32)"
205 range 2 32
206 depends on SMP
207 default 8
208 help
209 On multiprocessor machines, U-Boot sets up a stack for each CPU.
210 Stack memory is pre-allocated. U-Boot must therefore know the
211 maximum number of CPUs that may be present.
212
213config SBI_IPI
214 bool
215 default y if RISCV_SMODE || SPL_RISCV_SMODE
216 depends on SMP
217
218config XIP
219 bool "XIP mode"
220 help
221 XIP (eXecute In Place) is a method for executing code directly
222 from a NOR flash memory without copying the code to ram.
223 Say yes here if U-Boot boots from flash directly.
224
225config STACK_SIZE_SHIFT
226 int
227 default 14
228
229config SPL_LDSCRIPT
230 default "arch/riscv/cpu/u-boot-spl.lds"
231
232endmenu
233
