LXR uboot/arch/x86/cpu/broadwell/cpu

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (c) 2016 Google, Inc
   4 *
   5 * Based on code from coreboot src/soc/intel/broadwell/cpu.c
   6 */
   7
   8#include <common.h>
   9#include <dm.h>
  10#include <cpu.h>
  11#include <asm/cpu.h>
  12#include <asm/cpu_x86.h>
  13#include <asm/cpu_common.h>
  14#include <asm/intel_regs.h>
  15#include <asm/msr.h>
  16#include <asm/post.h>
  17#include <asm/turbo.h>
  18#include <asm/arch/cpu.h>
  19#include <asm/arch/pch.h>
  20#include <asm/arch/rcb.h>
  21
  22struct cpu_broadwell_priv {
  23        bool ht_disabled;
  24};
  25
  26/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
  27static const u8 power_limit_time_sec_to_msr[] = {
  28        [0]   = 0x00,
  29        [1]   = 0x0a,
  30        [2]   = 0x0b,
  31        [3]   = 0x4b,
  32        [4]   = 0x0c,
  33        [5]   = 0x2c,
  34        [6]   = 0x4c,
  35        [7]   = 0x6c,
  36        [8]   = 0x0d,
  37        [10]  = 0x2d,
  38        [12]  = 0x4d,
  39        [14]  = 0x6d,
  40        [16]  = 0x0e,
  41        [20]  = 0x2e,
  42        [24]  = 0x4e,
  43        [28]  = 0x6e,
  44        [32]  = 0x0f,
  45        [40]  = 0x2f,
  46        [48]  = 0x4f,
  47        [56]  = 0x6f,
  48        [64]  = 0x10,
  49        [80]  = 0x30,
  50        [96]  = 0x50,
  51        [112] = 0x70,
  52        [128] = 0x11,
  53};
  54
  55/* Convert POWER_LIMIT_1_TIME MSR value to seconds */
  56static const u8 power_limit_time_msr_to_sec[] = {
  57        [0x00] = 0,
  58        [0x0a] = 1,
  59        [0x0b] = 2,
  60        [0x4b] = 3,
  61        [0x0c] = 4,
  62        [0x2c] = 5,
  63        [0x4c] = 6,
  64        [0x6c] = 7,
  65        [0x0d] = 8,
  66        [0x2d] = 10,
  67        [0x4d] = 12,
  68        [0x6d] = 14,
  69        [0x0e] = 16,
  70        [0x2e] = 20,
  71        [0x4e] = 24,
  72        [0x6e] = 28,
  73        [0x0f] = 32,
  74        [0x2f] = 40,
  75        [0x4f] = 48,
  76        [0x6f] = 56,
  77        [0x10] = 64,
  78        [0x30] = 80,
  79        [0x50] = 96,
  80        [0x70] = 112,
  81        [0x11] = 128,
  82};
  83
  84#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
  85int arch_cpu_init(void)
  86{
  87        return 0;
  88}
  89#endif
  90
  91/*
  92 * The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate
  93 * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly
  94 * when a core is woken up
  95 */
  96static int pcode_ready(void)
  97{
  98        int wait_count;
  99        const int delay_step = 10;
 100
 101        wait_count = 0;
 102        do {
 103                if (!(readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) &
 104                                MAILBOX_RUN_BUSY))
 105                        return 0;
 106                wait_count += delay_step;
 107                udelay(delay_step);
 108        } while (wait_count < 1000);
 109
 110        return -ETIMEDOUT;
 111}
 112
 113static u32 pcode_mailbox_read(u32 command)
 114{
 115        int ret;
 116
 117        ret = pcode_ready();
 118        if (ret) {
 119                debug("PCODE: mailbox timeout on wait ready\n");
 120                return ret;
 121        }
 122
 123        /* Send command and start transaction */
 124        writel(command | MAILBOX_RUN_BUSY, MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
 125
 126        ret = pcode_ready();
 127        if (ret) {
 128                debug("PCODE: mailbox timeout on completion\n");
 129                return ret;
 130        }
 131
 132        /* Read mailbox */
 133        return readl(MCHBAR_REG(BIOS_MAILBOX_DATA));
 134}
 135
 136static int pcode_mailbox_write(u32 command, u32 data)
 137{
 138        int ret;
 139
 140        ret = pcode_ready();
 141        if (ret) {
 142                debug("PCODE: mailbox timeout on wait ready\n");
 143                return ret;
 144        }
 145
 146        writel(data, MCHBAR_REG(BIOS_MAILBOX_DATA));
 147
 148        /* Send command and start transaction */
 149        writel(command | MAILBOX_RUN_BUSY, MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
 150
 151        ret = pcode_ready();
 152        if (ret) {
 153                debug("PCODE: mailbox timeout on completion\n");
 154                return ret;
 155        }
 156
 157        return 0;
 158}
 159
 160/* @dev is the CPU device */
 161static void initialize_vr_config(struct udevice *dev)
 162{
 163        int ramp, min_vid;
 164        msr_t msr;
 165
 166        debug("Initializing VR config\n");
 167
 168        /* Configure VR_CURRENT_CONFIG */
 169        msr = msr_read(MSR_VR_CURRENT_CONFIG);
 170        /*
 171         * Preserve bits 63 and 62. Bit 62 is PSI4 enable, but it is only valid
 172         * on ULT systems
 173         */
 174        msr.hi &= 0xc0000000;
 175        msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold -  1A */
 176        msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold -  5A */
 177        msr.hi |= (0x14 << (32 - 32)); /* PSI1 threshold - 20A */
 178        msr.hi |= (1 <<  (62 - 32)); /* Enable PSI4 */
 179        /* Leave the max instantaneous current limit (12:0) to default */
 180        msr_write(MSR_VR_CURRENT_CONFIG, msr);
 181
 182        /* Configure VR_MISC_CONFIG MSR */
 183        msr = msr_read(MSR_VR_MISC_CONFIG);
 184        /* Set the IOUT_SLOPE scalar applied to dIout in U10.1.9 format */
 185        msr.hi &= ~(0x3ff << (40 - 32));
 186        msr.hi |= (0x200 << (40 - 32)); /* 1.0 */
 187        /* Set IOUT_OFFSET to 0 */
 188        msr.hi &= ~0xff;
 189        /* Set entry ramp rate to slow */
 190        msr.hi &= ~(1 << (51 - 32));
 191        /* Enable decay mode on C-state entry */
 192        msr.hi |= (1 << (52 - 32));
 193        /* Set the slow ramp rate */
 194        msr.hi &= ~(0x3 << (53 - 32));
 195        /* Configure the C-state exit ramp rate */
 196        ramp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 197                              "intel,slow-ramp", -1);
 198        if (ramp != -1) {
 199                /* Configured slow ramp rate */
 200                msr.hi |= ((ramp & 0x3) << (53 - 32));
 201                /* Set exit ramp rate to slow */
 202                msr.hi &= ~(1 << (50 - 32));
 203        } else {
 204                /* Fast ramp rate / 4 */
 205                msr.hi |= (0x01 << (53 - 32));
 206                /* Set exit ramp rate to fast */
 207                msr.hi |= (1 << (50 - 32));
 208        }
 209        /* Set MIN_VID (31:24) to allow CPU to have full control */
 210        msr.lo &= ~0xff000000;
 211        min_vid = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 212                                 "intel,min-vid", 0);
 213        msr.lo |= (min_vid & 0xff) << 24;
 214        msr_write(MSR_VR_MISC_CONFIG, msr);
 215
 216        /*  Configure VR_MISC_CONFIG2 MSR */
 217        msr = msr_read(MSR_VR_MISC_CONFIG2);
 218        msr.lo &= ~0xffff;
 219        /*
 220         * Allow CPU to control minimum voltage completely (15:8) and
 221         * set the fast ramp voltage in 10mV steps
 222         */
 223        if (cpu_get_family_model() == BROADWELL_FAMILY_ULT)
 224                msr.lo |= 0x006a; /* 1.56V */
 225        else
 226                msr.lo |= 0x006f; /* 1.60V */
 227        msr_write(MSR_VR_MISC_CONFIG2, msr);
 228
 229        /* Set C9/C10 VCC Min */
 230        pcode_mailbox_write(MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE, 0x1f1f);
 231}
 232
 233static int calibrate_24mhz_bclk(void)
 234{
 235        int err_code;
 236        int ret;
 237
 238        ret = pcode_ready();
 239        if (ret)
 240                return ret;
 241
 242        /* A non-zero value initiates the PCODE calibration */
 243        writel(~0, MCHBAR_REG(BIOS_MAILBOX_DATA));
 244        writel(MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL,
 245               MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
 246
 247        ret = pcode_ready();
 248        if (ret)
 249                return ret;
 250
 251        err_code = readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) & 0xff;
 252
 253        debug("PCODE: 24MHz BLCK calibration response: %d\n", err_code);
 254
 255        /* Read the calibrated value */
 256        writel(MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION,
 257               MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
 258
 259        ret = pcode_ready();
 260        if (ret)
 261                return ret;
 262
 263        debug("PCODE: 24MHz BLCK calibration value: 0x%08x\n",
 264              readl(MCHBAR_REG(BIOS_MAILBOX_DATA)));
 265
 266        return 0;
 267}
 268
 269static void configure_pch_power_sharing(void)
 270{
 271        u32 pch_power, pch_power_ext, pmsync, pmsync2;
 272        int i;
 273
 274        /* Read PCH Power levels from PCODE */
 275        pch_power = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER);
 276        pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT);
 277
 278        debug("PCH Power: PCODE Levels 0x%08x 0x%08x\n", pch_power,
 279              pch_power_ext);
 280
 281        pmsync = readl(RCB_REG(PMSYNC_CONFIG));
 282        pmsync2 = readl(RCB_REG(PMSYNC_CONFIG2));
 283
 284        /*
 285         * Program PMSYNC_TPR_CONFIG PCH power limit values
 286         *  pmsync[0:4]   = mailbox[0:5]
 287         *  pmsync[8:12]  = mailbox[6:11]
 288         *  pmsync[16:20] = mailbox[12:17]
 289         */
 290        for (i = 0; i < 3; i++) {
 291                u32 level = pch_power & 0x3f;
 292
 293                pch_power >>= 6;
 294                pmsync &= ~(0x1f << (i * 8));
 295                pmsync |= (level & 0x1f) << (i * 8);
 296        }
 297        writel(pmsync, RCB_REG(PMSYNC_CONFIG));
 298
 299        /*
 300         * Program PMSYNC_TPR_CONFIG2 Extended PCH power limit values
 301         *  pmsync2[0:4]   = mailbox[23:18]
 302         *  pmsync2[8:12]  = mailbox_ext[6:11]
 303         *  pmsync2[16:20] = mailbox_ext[12:17]
 304         *  pmsync2[24:28] = mailbox_ext[18:22]
 305         */
 306        pmsync2 &= ~0x1f;
 307        pmsync2 |= pch_power & 0x1f;
 308
 309        for (i = 1; i < 4; i++) {
 310                u32 level = pch_power_ext & 0x3f;
 311
 312                pch_power_ext >>= 6;
 313                pmsync2 &= ~(0x1f << (i * 8));
 314                pmsync2 |= (level & 0x1f) << (i * 8);
 315        }
 316        writel(pmsync2, RCB_REG(PMSYNC_CONFIG2));
 317}
 318
 319static int bsp_init_before_ap_bringup(struct udevice *dev)
 320{
 321        int ret;
 322
 323        initialize_vr_config(dev);
 324        ret = calibrate_24mhz_bclk();
 325        if (ret)
 326                return ret;
 327        configure_pch_power_sharing();
 328
 329        return 0;
 330}
 331
 332static void set_max_ratio(void)
 333{
 334        msr_t msr, perf_ctl;
 335
 336        perf_ctl.hi = 0;
 337
 338        /* Check for configurable TDP option */
 339        if (turbo_get_state() == TURBO_ENABLED) {
 340                msr = msr_read(MSR_TURBO_RATIO_LIMIT);
 341                perf_ctl.lo = (msr.lo & 0xff) << 8;
 342        } else if (cpu_config_tdp_levels()) {
 343                /* Set to nominal TDP ratio */
 344                msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
 345                perf_ctl.lo = (msr.lo & 0xff) << 8;
 346        } else {
 347                /* Platform Info bits 15:8 give max ratio */
 348                msr = msr_read(MSR_PLATFORM_INFO);
 349                perf_ctl.lo = msr.lo & 0xff00;
 350        }
 351        msr_write(MSR_IA32_PERF_CTL, perf_ctl);
 352
 353        debug("cpu: frequency set to %d\n",
 354              ((perf_ctl.lo >> 8) & 0xff) * INTEL_BCLK_MHZ);
 355}
 356
 357int broadwell_init(struct udevice *dev)
 358{
 359        struct cpu_broadwell_priv *priv = dev_get_priv(dev);
 360        int num_threads;
 361        int num_cores;
 362        msr_t msr;
 363        int ret;
 364
 365        msr = msr_read(CORE_THREAD_COUNT_MSR);
 366        num_threads = (msr.lo >> 0) & 0xffff;
 367        num_cores = (msr.lo >> 16) & 0xffff;
 368        debug("CPU has %u cores, %u threads enabled\n", num_cores,
 369              num_threads);
 370
 371        priv->ht_disabled = num_threads == num_cores;
 372
 373        ret = bsp_init_before_ap_bringup(dev);
 374        if (ret)
 375                return ret;
 376
 377        set_max_ratio();
 378
 379        return ret;
 380}
 381
 382static void configure_mca(void)
 383{
 384        msr_t msr;
 385        const unsigned int mcg_cap_msr = 0x179;
 386        int i;
 387        int num_banks;
 388
 389        msr = msr_read(mcg_cap_msr);
 390        num_banks = msr.lo & 0xff;
 391        msr.lo = 0;
 392        msr.hi = 0;
 393        /*
 394         * TODO(adurbin): This should only be done on a cold boot. Also, some
 395         * of these banks are core vs package scope. For now every CPU clears
 396         * every bank
 397         */
 398        for (i = 0; i < num_banks; i++)
 399                msr_write(MSR_IA32_MC0_STATUS + (i * 4), msr);
 400}
 401
 402static void enable_lapic_tpr(void)
 403{
 404        msr_t msr;
 405
 406        msr = msr_read(MSR_PIC_MSG_CONTROL);
 407        msr.lo &= ~(1 << 10);   /* Enable APIC TPR updates */
 408        msr_write(MSR_PIC_MSG_CONTROL, msr);
 409}
 410
 411static void configure_c_states(void)
 412{
 413        msr_t msr;
 414
 415        msr = msr_read(MSR_PMG_CST_CONFIG_CONTROL);
 416        msr.lo |= (1 << 31);    /* Timed MWAIT Enable */
 417        msr.lo |= (1 << 30);    /* Package c-state Undemotion Enable */
 418        msr.lo |= (1 << 29);    /* Package c-state Demotion Enable */
 419        msr.lo |= (1 << 28);    /* C1 Auto Undemotion Enable */
 420        msr.lo |= (1 << 27);    /* C3 Auto Undemotion Enable */
 421        msr.lo |= (1 << 26);    /* C1 Auto Demotion Enable */
 422        msr.lo |= (1 << 25);    /* C3 Auto Demotion Enable */
 423        msr.lo &= ~(1 << 10);   /* Disable IO MWAIT redirection */
 424        /* The deepest package c-state defaults to factory-configured value */
 425        msr_write(MSR_PMG_CST_CONFIG_CONTROL, msr);
 426
 427        msr = msr_read(MSR_MISC_PWR_MGMT);
 428        msr.lo &= ~(1 << 0);    /* Enable P-state HW_ALL coordination */
 429        msr_write(MSR_MISC_PWR_MGMT, msr);
 430
 431        msr = msr_read(MSR_POWER_CTL);
 432        msr.lo |= (1 << 18);    /* Enable Energy Perf Bias MSR 0x1b0 */
 433        msr.lo |= (1 << 1);     /* C1E Enable */
 434        msr.lo |= (1 << 0);     /* Bi-directional PROCHOT# */
 435        msr_write(MSR_POWER_CTL, msr);
 436
 437        /* C-state Interrupt Response Latency Control 0 - package C3 latency */
 438        msr.hi = 0;
 439        msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT;
 440        msr_write(MSR_C_STATE_LATENCY_CONTROL_0, msr);
 441
 442        /* C-state Interrupt Response Latency Control 1 */
 443        msr.hi = 0;
 444        msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT;
 445        msr_write(MSR_C_STATE_LATENCY_CONTROL_1, msr);
 446
 447        /* C-state Interrupt Response Latency Control 2 - package C6/C7 short */
 448        msr.hi = 0;
 449        msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT;
 450        msr_write(MSR_C_STATE_LATENCY_CONTROL_2, msr);
 451
 452        /* C-state Interrupt Response Latency Control 3 - package C8 */
 453        msr.hi = 0;
 454        msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT;
 455        msr_write(MSR_C_STATE_LATENCY_CONTROL_3, msr);
 456
 457        /* C-state Interrupt Response Latency Control 4 - package C9 */
 458        msr.hi = 0;
 459        msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT;
 460        msr_write(MSR_C_STATE_LATENCY_CONTROL_4, msr);
 461
 462        /* C-state Interrupt Response Latency Control 5 - package C10 */
 463        msr.hi = 0;
 464        msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT;
 465        msr_write(MSR_C_STATE_LATENCY_CONTROL_5, msr);
 466}
 467
 468static void configure_misc(void)
 469{
 470        msr_t msr;
 471
 472        msr = msr_read(MSR_IA32_MISC_ENABLE);
 473        msr.lo |= MISC_ENABLE_FAST_STRING;
 474        msr.lo |= MISC_ENABLE_TM1;
 475        msr.lo |= MISC_ENABLE_ENHANCED_SPEEDSTEP;
 476        msr_write(MSR_IA32_MISC_ENABLE, msr);
 477
 478        /* Disable thermal interrupts */
 479        msr.lo = 0;
 480        msr.hi = 0;
 481        msr_write(MSR_IA32_THERM_INTERRUPT, msr);
 482
 483        /* Enable package critical interrupt only */
 484        msr.lo = 1 << 4;
 485        msr.hi = 0;
 486        msr_write(MSR_IA32_PACKAGE_THERM_INTERRUPT, msr);
 487}
 488
 489static void configure_dca_cap(void)
 490{
 491        struct cpuid_result cpuid_regs;
 492        msr_t msr;
 493
 494        /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
 495        cpuid_regs = cpuid(1);
 496        if (cpuid_regs.ecx & (1 << 18)) {
 497                msr = msr_read(MSR_IA32_PLATFORM_DCA_CAP);
 498                msr.lo |= 1;
 499                msr_write(MSR_IA32_PLATFORM_DCA_CAP, msr);
 500        }
 501}
 502
 503static void set_energy_perf_bias(u8 policy)
 504{
 505        msr_t msr;
 506        int ecx;
 507
 508        /* Determine if energy efficient policy is supported */
 509        ecx = cpuid_ecx(0x6);
 510        if (!(ecx & (1 << 3)))
 511                return;
 512
 513        /* Energy Policy is bits 3:0 */
 514        msr = msr_read(MSR_IA32_ENERGY_PERFORMANCE_BIAS);
 515        msr.lo &= ~0xf;
 516        msr.lo |= policy & 0xf;
 517        msr_write(MSR_IA32_ENERGY_PERFORMANCE_BIAS, msr);
 518
 519        debug("cpu: energy policy set to %u\n", policy);
 520}
 521
 522/* All CPUs including BSP will run the following function */
 523static void cpu_core_init(struct udevice *dev)
 524{
 525        /* Clear out pending MCEs */
 526        configure_mca();
 527
 528        /* Enable the local cpu apics */
 529        enable_lapic_tpr();
 530
 531        /* Configure C States */
 532        configure_c_states();
 533
 534        /* Configure Enhanced SpeedStep and Thermal Sensors */
 535        configure_misc();
 536
 537        /* Thermal throttle activation offset */
 538        cpu_configure_thermal_target(dev);
 539
 540        /* Enable Direct Cache Access */
 541        configure_dca_cap();
 542
 543        /* Set energy policy */
 544        set_energy_perf_bias(ENERGY_POLICY_NORMAL);
 545
 546        /* Enable Turbo */
 547        turbo_enable();
 548}
 549
 550/*
 551 * Configure processor power limits if possible
 552 * This must be done AFTER set of BIOS_RESET_CPL
 553 */
 554void cpu_set_power_limits(int power_limit_1_time)
 555{
 556        msr_t msr;
 557        msr_t limit;
 558        uint power_unit;
 559        uint tdp, min_power, max_power, max_time;
 560        u8 power_limit_1_val;
 561
 562        msr = msr_read(MSR_PLATFORM_INFO);
 563        if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
 564                power_limit_1_time = 28;
 565
 566        if (!(msr.lo & PLATFORM_INFO_SET_TDP))
 567                return;
 568
 569        /* Get units */
 570        msr = msr_read(MSR_PKG_POWER_SKU_UNIT);
 571        power_unit = 2 << ((msr.lo & 0xf) - 1);
 572
 573        /* Get power defaults for this SKU */
 574        msr = msr_read(MSR_PKG_POWER_SKU);
 575        tdp = msr.lo & 0x7fff;
 576        min_power = (msr.lo >> 16) & 0x7fff;
 577        max_power = msr.hi & 0x7fff;
 578        max_time = (msr.hi >> 16) & 0x7f;
 579
 580        debug("CPU TDP: %u Watts\n", tdp / power_unit);
 581
 582        if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
 583                power_limit_1_time = power_limit_time_msr_to_sec[max_time];
 584
 585        if (min_power > 0 && tdp < min_power)
 586                tdp = min_power;
 587
 588        if (max_power > 0 && tdp > max_power)
 589                tdp = max_power;
 590
 591        power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
 592
 593        /* Set long term power limit to TDP */
 594        limit.lo = 0;
 595        limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
 596        limit.lo |= PKG_POWER_LIMIT_EN;
 597        limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
 598                PKG_POWER_LIMIT_TIME_SHIFT;
 599
 600        /* Set short term power limit to 1.25 * TDP */
 601        limit.hi = 0;
 602        limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
 603        limit.hi |= PKG_POWER_LIMIT_EN;
 604        /* Power limit 2 time is only programmable on server SKU */
 605
 606        msr_write(MSR_PKG_POWER_LIMIT, limit);
 607
 608        /* Set power limit values in MCHBAR as well */
 609        writel(limit.lo, MCHBAR_REG(MCH_PKG_POWER_LIMIT_LO));
 610        writel(limit.hi, MCHBAR_REG(MCH_PKG_POWER_LIMIT_HI));
 611
 612        /* Set DDR RAPL power limit by copying from MMIO to MSR */
 613        msr.lo = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_LO));
 614        msr.hi = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_HI));
 615        msr_write(MSR_DDR_RAPL_LIMIT, msr);
 616
 617        /* Use nominal TDP values for CPUs with configurable TDP */
 618        if (cpu_config_tdp_levels()) {
 619                msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
 620                limit.hi = 0;
 621                limit.lo = msr.lo & 0xff;
 622                msr_write(MSR_TURBO_ACTIVATION_RATIO, limit);
 623        }
 624}
 625
 626static int broadwell_get_info(struct udevice *dev, struct cpu_info *info)
 627{
 628        return cpu_intel_get_info(info, INTEL_BCLK_MHZ);
 629}
 630
 631static int broadwell_get_count(struct udevice *dev)
 632{
 633        return 4;
 634}
 635
 636static int cpu_x86_broadwell_probe(struct udevice *dev)
 637{
 638        if (dev->seq == 0) {
 639                cpu_core_init(dev);
 640                return broadwell_init(dev);
 641        }
 642
 643        return 0;
 644}
 645
 646static const struct cpu_ops cpu_x86_broadwell_ops = {
 647        .get_desc       = cpu_x86_get_desc,
 648        .get_info       = broadwell_get_info,
 649        .get_count      = broadwell_get_count,
 650        .get_vendor     = cpu_x86_get_vendor,
 651};
 652
 653static const struct udevice_id cpu_x86_broadwell_ids[] = {
 654        { .compatible = "intel,core-i3-gen5" },
 655        { }
 656};
 657
 658U_BOOT_DRIVER(cpu_x86_broadwell_drv) = {
 659        .name           = "cpu_x86_broadwell",
 660        .id             = UCLASS_CPU,
 661        .of_match       = cpu_x86_broadwell_ids,
 662        .bind           = cpu_x86_bind,
 663        .probe          = cpu_x86_broadwell_probe,
 664        .ops            = &cpu_x86_broadwell_ops,
 665        .priv_auto_alloc_size   = sizeof(struct cpu_broadwell_priv),
 666        .flags          = DM_FLAG_PRE_RELOC,
 667};
 668