LXR uboot/board/freescale/m5275evb/m5275evb.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2000-2003
   4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5 *
   6 * Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com)
   7 *
   8 * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
   9 */
  10
  11#include <common.h>
  12#include <asm/immap.h>
  13#include <asm/io.h>
  14
  15DECLARE_GLOBAL_DATA_PTR;
  16
  17#define PERIOD          13      /* system bus period in ns */
  18#define SDRAM_TREFI     7800    /* in ns */
  19
  20int checkboard(void)
  21{
  22        puts("Board: ");
  23        puts("Freescale MCF5275 EVB\n");
  24        return 0;
  25};
  26
  27int dram_init(void)
  28{
  29        sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
  30        gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
  31
  32        /* Enable SDRAM */
  33        out_be16(&gpio_reg->par_sdram, 0x3FF);
  34
  35        /* Set up chip select */
  36        out_be32(&sdp->sdbar0, CONFIG_SYS_SDRAM_BASE);
  37        out_be32(&sdp->sdbmr0, MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V);
  38
  39        /* Set up timing */
  40        out_be32(&sdp->sdcfg1, 0x83711630);
  41        out_be32(&sdp->sdcfg2, 0x46770000);
  42
  43        /* Enable clock */
  44        out_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE);
  45
  46        /* Set precharge */
  47        setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
  48
  49        /* Dummy write to start SDRAM */
  50        *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
  51
  52        /* Send LEMR */
  53        setbits_be32(&sdp->sdmr,
  54                MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_AD(0x0) |
  55                MCF_SDRAMC_SDMR_CMD);
  56        *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
  57
  58        /* Send LMR */
  59        out_be32(&sdp->sdmr, 0x058d0000);
  60        *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
  61
  62        /* Stop sending commands */
  63        clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
  64
  65        /* Set precharge */
  66        setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
  67        *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
  68
  69        /* Stop manual precharge, send 2 IREF */
  70        clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
  71        setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IREF);
  72        *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
  73        *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
  74
  75
  76        out_be32(&sdp->sdmr, 0x018d0000);
  77        *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
  78
  79        /* Stop sending commands */
  80        clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
  81        clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN);
  82
  83        /* Turn on auto refresh, lock SDMR */
  84        out_be32(&sdp->sdcr,
  85                MCF_SDRAMC_SDCR_CKE
  86                | MCF_SDRAMC_SDCR_REF
  87                | MCF_SDRAMC_SDCR_MUX(1)
  88                /* 1 added to round up */
  89                | MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
  90                | MCF_SDRAMC_SDCR_DQS_OE(0x3));
  91
  92        gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  93
  94        return 0;
  95};
  96
  97int testdram(void)
  98{
  99        /* TODO: XXX XXX XXX */
 100        printf("DRAM test not implemented!\n");
 101
 102        return (0);
 103}
 104