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8#include <init.h>
9#include <asm/arch/clock.h>
10#include <asm/arch/imx-regs.h>
11#include <asm/arch/iomux.h>
12#include <asm/arch/mx6-pins.h>
13#include <asm/mach-imx/spi.h>
14#include <env.h>
15#include <linux/errno.h>
16#include <asm/gpio.h>
17#include <asm/mach-imx/mxc_i2c.h>
18#include <asm/mach-imx/iomux-v3.h>
19#include <asm/mach-imx/boot_mode.h>
20#include <asm/mach-imx/video.h>
21#include <mmc.h>
22#include <fsl_esdhc_imx.h>
23#include <miiphy.h>
24#include <netdev.h>
25#include <asm/arch/mxc_hdmi.h>
26#include <asm/arch/crm_regs.h>
27#include <asm/io.h>
28#include <asm/arch/sys_proto.h>
29#include <i2c.h>
30#include <input.h>
31#include <power/pmic.h>
32#include <power/pfuze100_pmic.h>
33#include "../common/pfuze.h"
34#include <usb.h>
35#include <usb/ehci-ci.h>
36
37DECLARE_GLOBAL_DATA_PTR;
38
39#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
40 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
41 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
42
43#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
44 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
45 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
46
47#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
48 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
49
50#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
51 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
52
53#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
54 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
55 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
56
57#define I2C_PMIC 1
58
59#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
60
61#define DISP0_PWR_EN IMX_GPIO_NR(1, 21)
62
63#define KEY_VOL_UP IMX_GPIO_NR(1, 4)
64
65int dram_init(void)
66{
67 gd->ram_size = imx_ddr_size();
68 return 0;
69}
70
71static iomux_v3_cfg_t const uart1_pads[] = {
72 IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
73 IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
74};
75
76static iomux_v3_cfg_t const enet_pads[] = {
77 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
78 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
79 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
80 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
81 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
82 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
83 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
84 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
85 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
86 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
87 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
88 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
89 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
90 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
91 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
92
93 IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
94};
95
96static void setup_iomux_enet(void)
97{
98 SETUP_IOMUX_PADS(enet_pads);
99}
100
101static iomux_v3_cfg_t const usdhc2_pads[] = {
102 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
103 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
104 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
105 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
106 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
107 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
108 IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
109 IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
110 IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
111 IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
112 IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
113};
114
115static iomux_v3_cfg_t const usdhc3_pads[] = {
116 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
117 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
118 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
119 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
120 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
121 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
122 IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
123 IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
124 IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
125 IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
126 IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
127};
128
129static iomux_v3_cfg_t const usdhc4_pads[] = {
130 IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
131 IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
132 IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
133 IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
134 IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
135 IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
136 IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
137 IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
138 IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
139 IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
140};
141
142static iomux_v3_cfg_t const ecspi1_pads[] = {
143 IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
144 IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
145 IOMUX_PADS(PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
146 IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
147};
148
149static iomux_v3_cfg_t const rgb_pads[] = {
150 IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
151 IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
152 IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
153 IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
154 IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
155 IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
156 IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
157 IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
158 IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
159 IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
160 IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
161 IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
162 IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
163 IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
164 IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
165 IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL)),
166 IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
167 IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
168 IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
169 IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
170 IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
171 IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
172 IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL)),
173 IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
174 IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
175 IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
176 IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
177 IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL)),
178 IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
179};
180
181static iomux_v3_cfg_t const bl_pads[] = {
182 IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
183};
184
185static void enable_backlight(void)
186{
187 SETUP_IOMUX_PADS(bl_pads);
188 gpio_request(DISP0_PWR_EN, "Display Power Enable");
189 gpio_direction_output(DISP0_PWR_EN, 1);
190}
191
192static void enable_rgb(struct display_info_t const *dev)
193{
194 SETUP_IOMUX_PADS(rgb_pads);
195 enable_backlight();
196}
197
198static void enable_lvds(struct display_info_t const *dev)
199{
200 enable_backlight();
201}
202
203static struct i2c_pads_info mx6q_i2c_pad_info1 = {
204 .scl = {
205 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
206 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
207 .gp = IMX_GPIO_NR(4, 12)
208 },
209 .sda = {
210 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
211 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
212 .gp = IMX_GPIO_NR(4, 13)
213 }
214};
215
216static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
217 .scl = {
218 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
219 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
220 .gp = IMX_GPIO_NR(4, 12)
221 },
222 .sda = {
223 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
224 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
225 .gp = IMX_GPIO_NR(4, 13)
226 }
227};
228
229static void setup_spi(void)
230{
231 SETUP_IOMUX_PADS(ecspi1_pads);
232}
233
234iomux_v3_cfg_t const pcie_pads[] = {
235 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
236 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
237};
238
239static void setup_pcie(void)
240{
241 SETUP_IOMUX_PADS(pcie_pads);
242}
243
244iomux_v3_cfg_t const di0_pads[] = {
245 IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
246 IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02),
247 IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03),
248};
249
250static void setup_iomux_uart(void)
251{
252 SETUP_IOMUX_PADS(uart1_pads);
253}
254
255#ifdef CONFIG_FSL_ESDHC_IMX
256struct fsl_esdhc_cfg usdhc_cfg[3] = {
257 {USDHC2_BASE_ADDR},
258 {USDHC3_BASE_ADDR},
259 {USDHC4_BASE_ADDR},
260};
261
262#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
263#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
264
265int board_mmc_get_env_dev(int devno)
266{
267 return devno - 1;
268}
269
270int board_mmc_getcd(struct mmc *mmc)
271{
272 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
273 int ret = 0;
274
275 switch (cfg->esdhc_base) {
276 case USDHC2_BASE_ADDR:
277 ret = !gpio_get_value(USDHC2_CD_GPIO);
278 break;
279 case USDHC3_BASE_ADDR:
280 ret = !gpio_get_value(USDHC3_CD_GPIO);
281 break;
282 case USDHC4_BASE_ADDR:
283 ret = 1;
284 break;
285 }
286
287 return ret;
288}
289
290int board_mmc_init(bd_t *bis)
291{
292 struct src *psrc = (struct src *)SRC_BASE_ADDR;
293 unsigned reg = readl(&psrc->sbmr1) >> 11;
294
295
296
297
298
299
300
301
302
303 switch (reg & 0x3) {
304 case 0x1:
305 SETUP_IOMUX_PADS(usdhc2_pads);
306 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
307 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
308 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
309 break;
310 case 0x2:
311 SETUP_IOMUX_PADS(usdhc3_pads);
312 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
313 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
314 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
315 break;
316 case 0x3:
317 SETUP_IOMUX_PADS(usdhc4_pads);
318 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
319 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
320 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
321 break;
322 }
323
324 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
325}
326#endif
327
328static int ar8031_phy_fixup(struct phy_device *phydev)
329{
330 unsigned short val;
331
332
333 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
334 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
335 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
336
337 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
338 val &= 0xffe3;
339 val |= 0x18;
340 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
341
342
343 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
344 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
345 val |= 0x0100;
346 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
347
348 return 0;
349}
350
351int board_phy_config(struct phy_device *phydev)
352{
353 ar8031_phy_fixup(phydev);
354
355 if (phydev->drv->config)
356 phydev->drv->config(phydev);
357
358 return 0;
359}
360
361#if defined(CONFIG_VIDEO_IPUV3)
362static void disable_lvds(struct display_info_t const *dev)
363{
364 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
365
366 int reg = readl(&iomux->gpr[2]);
367
368 reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
369 IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
370
371 writel(reg, &iomux->gpr[2]);
372}
373
374static void do_enable_hdmi(struct display_info_t const *dev)
375{
376 disable_lvds(dev);
377 imx_enable_hdmi_phy();
378}
379
380struct display_info_t const displays[] = {{
381 .bus = -1,
382 .addr = 0,
383 .pixfmt = IPU_PIX_FMT_RGB666,
384 .detect = NULL,
385 .enable = enable_lvds,
386 .mode = {
387 .name = "Hannstar-XGA",
388 .refresh = 60,
389 .xres = 1024,
390 .yres = 768,
391 .pixclock = 15384,
392 .left_margin = 160,
393 .right_margin = 24,
394 .upper_margin = 29,
395 .lower_margin = 3,
396 .hsync_len = 136,
397 .vsync_len = 6,
398 .sync = FB_SYNC_EXT,
399 .vmode = FB_VMODE_NONINTERLACED
400} }, {
401 .bus = -1,
402 .addr = 0,
403 .pixfmt = IPU_PIX_FMT_RGB24,
404 .detect = detect_hdmi,
405 .enable = do_enable_hdmi,
406 .mode = {
407 .name = "HDMI",
408 .refresh = 60,
409 .xres = 1024,
410 .yres = 768,
411 .pixclock = 15384,
412 .left_margin = 160,
413 .right_margin = 24,
414 .upper_margin = 29,
415 .lower_margin = 3,
416 .hsync_len = 136,
417 .vsync_len = 6,
418 .sync = FB_SYNC_EXT,
419 .vmode = FB_VMODE_NONINTERLACED
420} }, {
421 .bus = 0,
422 .addr = 0,
423 .pixfmt = IPU_PIX_FMT_RGB24,
424 .detect = NULL,
425 .enable = enable_rgb,
426 .mode = {
427 .name = "SEIKO-WVGA",
428 .refresh = 60,
429 .xres = 800,
430 .yres = 480,
431 .pixclock = 29850,
432 .left_margin = 89,
433 .right_margin = 164,
434 .upper_margin = 23,
435 .lower_margin = 10,
436 .hsync_len = 10,
437 .vsync_len = 10,
438 .sync = 0,
439 .vmode = FB_VMODE_NONINTERLACED
440} } };
441size_t display_count = ARRAY_SIZE(displays);
442
443static void setup_display(void)
444{
445 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
446 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
447 int reg;
448
449
450 SETUP_IOMUX_PADS(di0_pads);
451
452 enable_ipu_clock();
453 imx_setup_hdmi();
454
455
456 reg = readl(&mxc_ccm->CCGR3);
457 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
458 writel(reg, &mxc_ccm->CCGR3);
459
460
461 reg = readl(&mxc_ccm->cs2cdr);
462 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
463 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
464 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
465 | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
466 writel(reg, &mxc_ccm->cs2cdr);
467
468 reg = readl(&mxc_ccm->cscmr2);
469 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
470 writel(reg, &mxc_ccm->cscmr2);
471
472 reg = readl(&mxc_ccm->chsccdr);
473 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
474 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
475 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
476 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
477 writel(reg, &mxc_ccm->chsccdr);
478
479 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
480 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
481 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
482 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
483 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
484 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
485 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
486 | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
487 | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
488 writel(reg, &iomux->gpr[2]);
489
490 reg = readl(&iomux->gpr[3]);
491 reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
492 | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
493 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
494 << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
495 writel(reg, &iomux->gpr[3]);
496}
497#endif
498
499
500
501
502
503int overwrite_console(void)
504{
505 return 1;
506}
507
508int board_eth_init(bd_t *bis)
509{
510 setup_iomux_enet();
511 setup_pcie();
512
513 return cpu_eth_init(bis);
514}
515
516#ifdef CONFIG_USB_EHCI_MX6
517static void setup_usb(void)
518{
519
520
521
522
523 imx_iomux_set_gpr_register(1, 13, 1, 0);
524}
525#endif
526
527int board_early_init_f(void)
528{
529 setup_iomux_uart();
530
531 return 0;
532}
533
534int board_init(void)
535{
536
537 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
538
539#ifdef CONFIG_MXC_SPI
540 setup_spi();
541#endif
542 if (is_mx6dq() || is_mx6dqp())
543 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
544 else
545 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
546#if defined(CONFIG_VIDEO_IPUV3)
547 setup_display();
548#endif
549#ifdef CONFIG_USB_EHCI_MX6
550 setup_usb();
551#endif
552
553 return 0;
554}
555
556int power_init_board(void)
557{
558 struct pmic *p;
559 unsigned int reg;
560 int ret;
561
562 p = pfuze_common_init(I2C_PMIC);
563 if (!p)
564 return -ENODEV;
565
566 ret = pfuze_mode_init(p, APS_PFM);
567 if (ret < 0)
568 return ret;
569
570
571 pmic_reg_read(p, PFUZE100_VGEN3VOL, ®);
572 reg &= ~LDO_VOL_MASK;
573 reg |= LDOB_2_80V;
574 pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
575
576
577 pmic_reg_read(p, PFUZE100_VGEN5VOL, ®);
578 reg &= ~LDO_VOL_MASK;
579 reg |= LDOB_3_00V;
580 pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
581
582 return 0;
583}
584
585#ifdef CONFIG_MXC_SPI
586int board_spi_cs_gpio(unsigned bus, unsigned cs)
587{
588 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
589}
590#endif
591
592#ifdef CONFIG_CMD_BMODE
593static const struct boot_mode board_boot_modes[] = {
594
595 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
596 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
597
598 {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
599 {NULL, 0},
600};
601#endif
602
603int board_late_init(void)
604{
605#ifdef CONFIG_CMD_BMODE
606 add_board_boot_modes(board_boot_modes);
607#endif
608
609#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
610 env_set("board_name", "SABRESD");
611
612 if (is_mx6dqp())
613 env_set("board_rev", "MX6QP");
614 else if (is_mx6dq())
615 env_set("board_rev", "MX6Q");
616 else if (is_mx6sdl())
617 env_set("board_rev", "MX6DL");
618#endif
619
620 return 0;
621}
622
623int checkboard(void)
624{
625 puts("Board: MX6-SabreSD\n");
626 return 0;
627}
628
629#ifdef CONFIG_SPL_BUILD
630#include <asm/arch/mx6-ddr.h>
631#include <spl.h>
632#include <linux/libfdt.h>
633
634#ifdef CONFIG_SPL_OS_BOOT
635int spl_start_uboot(void)
636{
637 gpio_request(KEY_VOL_UP, "KEY Volume UP");
638 gpio_direction_input(KEY_VOL_UP);
639
640
641 return gpio_get_value(KEY_VOL_UP);
642}
643#endif
644
645static void ccgr_init(void)
646{
647 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
648
649 writel(0x00C03F3F, &ccm->CCGR0);
650 writel(0x0030FC03, &ccm->CCGR1);
651 writel(0x0FFFC000, &ccm->CCGR2);
652 writel(0x3FF00000, &ccm->CCGR3);
653 writel(0x00FFF300, &ccm->CCGR4);
654 writel(0x0F0000C3, &ccm->CCGR5);
655 writel(0x000003FF, &ccm->CCGR6);
656}
657
658static int mx6q_dcd_table[] = {
659 0x020e0798, 0x000C0000,
660 0x020e0758, 0x00000000,
661 0x020e0588, 0x00000030,
662 0x020e0594, 0x00000030,
663 0x020e056c, 0x00000030,
664 0x020e0578, 0x00000030,
665 0x020e074c, 0x00000030,
666 0x020e057c, 0x00000030,
667 0x020e058c, 0x00000000,
668 0x020e059c, 0x00000030,
669 0x020e05a0, 0x00000030,
670 0x020e078c, 0x00000030,
671 0x020e0750, 0x00020000,
672 0x020e05a8, 0x00000030,
673 0x020e05b0, 0x00000030,
674 0x020e0524, 0x00000030,
675 0x020e051c, 0x00000030,
676 0x020e0518, 0x00000030,
677 0x020e050c, 0x00000030,
678 0x020e05b8, 0x00000030,
679 0x020e05c0, 0x00000030,
680 0x020e0774, 0x00020000,
681 0x020e0784, 0x00000030,
682 0x020e0788, 0x00000030,
683 0x020e0794, 0x00000030,
684 0x020e079c, 0x00000030,
685 0x020e07a0, 0x00000030,
686 0x020e07a4, 0x00000030,
687 0x020e07a8, 0x00000030,
688 0x020e0748, 0x00000030,
689 0x020e05ac, 0x00000030,
690 0x020e05b4, 0x00000030,
691 0x020e0528, 0x00000030,
692 0x020e0520, 0x00000030,
693 0x020e0514, 0x00000030,
694 0x020e0510, 0x00000030,
695 0x020e05bc, 0x00000030,
696 0x020e05c4, 0x00000030,
697 0x021b0800, 0xa1390003,
698 0x021b080c, 0x001F001F,
699 0x021b0810, 0x001F001F,
700 0x021b480c, 0x001F001F,
701 0x021b4810, 0x001F001F,
702 0x021b083c, 0x43270338,
703 0x021b0840, 0x03200314,
704 0x021b483c, 0x431A032F,
705 0x021b4840, 0x03200263,
706 0x021b0848, 0x4B434748,
707 0x021b4848, 0x4445404C,
708 0x021b0850, 0x38444542,
709 0x021b4850, 0x4935493A,
710 0x021b081c, 0x33333333,
711 0x021b0820, 0x33333333,
712 0x021b0824, 0x33333333,
713 0x021b0828, 0x33333333,
714 0x021b481c, 0x33333333,
715 0x021b4820, 0x33333333,
716 0x021b4824, 0x33333333,
717 0x021b4828, 0x33333333,
718 0x021b08b8, 0x00000800,
719 0x021b48b8, 0x00000800,
720 0x021b0004, 0x00020036,
721 0x021b0008, 0x09444040,
722 0x021b000c, 0x555A7975,
723 0x021b0010, 0xFF538F64,
724 0x021b0014, 0x01FF00DB,
725 0x021b0018, 0x00001740,
726 0x021b001c, 0x00008000,
727 0x021b002c, 0x000026d2,
728 0x021b0030, 0x005A1023,
729 0x021b0040, 0x00000027,
730 0x021b0000, 0x831A0000,
731 0x021b001c, 0x04088032,
732 0x021b001c, 0x00008033,
733 0x021b001c, 0x00048031,
734 0x021b001c, 0x09408030,
735 0x021b001c, 0x04008040,
736 0x021b0020, 0x00005800,
737 0x021b0818, 0x00011117,
738 0x021b4818, 0x00011117,
739 0x021b0004, 0x00025576,
740 0x021b0404, 0x00011006,
741 0x021b001c, 0x00000000,
742};
743
744static int mx6qp_dcd_table[] = {
745 0x020e0798, 0x000c0000,
746 0x020e0758, 0x00000000,
747 0x020e0588, 0x00000030,
748 0x020e0594, 0x00000030,
749 0x020e056c, 0x00000030,
750 0x020e0578, 0x00000030,
751 0x020e074c, 0x00000030,
752 0x020e057c, 0x00000030,
753 0x020e058c, 0x00000000,
754 0x020e059c, 0x00000030,
755 0x020e05a0, 0x00000030,
756 0x020e078c, 0x00000030,
757 0x020e0750, 0x00020000,
758 0x020e05a8, 0x00000030,
759 0x020e05b0, 0x00000030,
760 0x020e0524, 0x00000030,
761 0x020e051c, 0x00000030,
762 0x020e0518, 0x00000030,
763 0x020e050c, 0x00000030,
764 0x020e05b8, 0x00000030,
765 0x020e05c0, 0x00000030,
766 0x020e0774, 0x00020000,
767 0x020e0784, 0x00000030,
768 0x020e0788, 0x00000030,
769 0x020e0794, 0x00000030,
770 0x020e079c, 0x00000030,
771 0x020e07a0, 0x00000030,
772 0x020e07a4, 0x00000030,
773 0x020e07a8, 0x00000030,
774 0x020e0748, 0x00000030,
775 0x020e05ac, 0x00000030,
776 0x020e05b4, 0x00000030,
777 0x020e0528, 0x00000030,
778 0x020e0520, 0x00000030,
779 0x020e0514, 0x00000030,
780 0x020e0510, 0x00000030,
781 0x020e05bc, 0x00000030,
782 0x020e05c4, 0x00000030,
783 0x021b0800, 0xa1390003,
784 0x021b080c, 0x001b001e,
785 0x021b0810, 0x002e0029,
786 0x021b480c, 0x001b002a,
787 0x021b4810, 0x0019002c,
788 0x021b083c, 0x43240334,
789 0x021b0840, 0x0324031a,
790 0x021b483c, 0x43340344,
791 0x021b4840, 0x03280276,
792 0x021b0848, 0x44383A3E,
793 0x021b4848, 0x3C3C3846,
794 0x021b0850, 0x2e303230,
795 0x021b4850, 0x38283E34,
796 0x021b081c, 0x33333333,
797 0x021b0820, 0x33333333,
798 0x021b0824, 0x33333333,
799 0x021b0828, 0x33333333,
800 0x021b481c, 0x33333333,
801 0x021b4820, 0x33333333,
802 0x021b4824, 0x33333333,
803 0x021b4828, 0x33333333,
804 0x021b08c0, 0x24912249,
805 0x021b48c0, 0x24914289,
806 0x021b08b8, 0x00000800,
807 0x021b48b8, 0x00000800,
808 0x021b0004, 0x00020036,
809 0x021b0008, 0x24444040,
810 0x021b000c, 0x555A7955,
811 0x021b0010, 0xFF320F64,
812 0x021b0014, 0x01ff00db,
813 0x021b0018, 0x00001740,
814 0x021b001c, 0x00008000,
815 0x021b002c, 0x000026d2,
816 0x021b0030, 0x005A1023,
817 0x021b0040, 0x00000027,
818 0x021b0400, 0x14420000,
819 0x021b0000, 0x831A0000,
820 0x021b0890, 0x00400C58,
821 0x00bb0008, 0x00000000,
822 0x00bb000c, 0x2891E41A,
823 0x00bb0038, 0x00000564,
824 0x00bb0014, 0x00000040,
825 0x00bb0028, 0x00000020,
826 0x00bb002c, 0x00000020,
827 0x021b001c, 0x04088032,
828 0x021b001c, 0x00008033,
829 0x021b001c, 0x00048031,
830 0x021b001c, 0x09408030,
831 0x021b001c, 0x04008040,
832 0x021b0020, 0x00005800,
833 0x021b0818, 0x00011117,
834 0x021b4818, 0x00011117,
835 0x021b0004, 0x00025576,
836 0x021b0404, 0x00011006,
837 0x021b001c, 0x00000000,
838};
839
840static int mx6dl_dcd_table[] = {
841 0x020e0774, 0x000C0000,
842 0x020e0754, 0x00000000,
843 0x020e04ac, 0x00000030,
844 0x020e04b0, 0x00000030,
845 0x020e0464, 0x00000030,
846 0x020e0490, 0x00000030,
847 0x020e074c, 0x00000030,
848 0x020e0494, 0x00000030,
849 0x020e04a0, 0x00000000,
850 0x020e04b4, 0x00000030,
851 0x020e04b8, 0x00000030,
852 0x020e076c, 0x00000030,
853 0x020e0750, 0x00020000,
854 0x020e04bc, 0x00000030,
855 0x020e04c0, 0x00000030,
856 0x020e04c4, 0x00000030,
857 0x020e04c8, 0x00000030,
858 0x020e04cc, 0x00000030,
859 0x020e04d0, 0x00000030,
860 0x020e04d4, 0x00000030,
861 0x020e04d8, 0x00000030,
862 0x020e0760, 0x00020000,
863 0x020e0764, 0x00000030,
864 0x020e0770, 0x00000030,
865 0x020e0778, 0x00000030,
866 0x020e077c, 0x00000030,
867 0x020e0780, 0x00000030,
868 0x020e0784, 0x00000030,
869 0x020e078c, 0x00000030,
870 0x020e0748, 0x00000030,
871 0x020e0470, 0x00000030,
872 0x020e0474, 0x00000030,
873 0x020e0478, 0x00000030,
874 0x020e047c, 0x00000030,
875 0x020e0480, 0x00000030,
876 0x020e0484, 0x00000030,
877 0x020e0488, 0x00000030,
878 0x020e048c, 0x00000030,
879 0x021b0800, 0xa1390003,
880 0x021b080c, 0x001F001F,
881 0x021b0810, 0x001F001F,
882 0x021b480c, 0x001F001F,
883 0x021b4810, 0x001F001F,
884 0x021b083c, 0x4220021F,
885 0x021b0840, 0x0207017E,
886 0x021b483c, 0x4201020C,
887 0x021b4840, 0x01660172,
888 0x021b0848, 0x4A4D4E4D,
889 0x021b4848, 0x4A4F5049,
890 0x021b0850, 0x3F3C3D31,
891 0x021b4850, 0x3238372B,
892 0x021b081c, 0x33333333,
893 0x021b0820, 0x33333333,
894 0x021b0824, 0x33333333,
895 0x021b0828, 0x33333333,
896 0x021b481c, 0x33333333,
897 0x021b4820, 0x33333333,
898 0x021b4824, 0x33333333,
899 0x021b4828, 0x33333333,
900 0x021b08b8, 0x00000800,
901 0x021b48b8, 0x00000800,
902 0x021b0004, 0x0002002D,
903 0x021b0008, 0x00333030,
904 0x021b000c, 0x3F435313,
905 0x021b0010, 0xB66E8B63,
906 0x021b0014, 0x01FF00DB,
907 0x021b0018, 0x00001740,
908 0x021b001c, 0x00008000,
909 0x021b002c, 0x000026d2,
910 0x021b0030, 0x00431023,
911 0x021b0040, 0x00000027,
912 0x021b0000, 0x831A0000,
913 0x021b001c, 0x04008032,
914 0x021b001c, 0x00008033,
915 0x021b001c, 0x00048031,
916 0x021b001c, 0x05208030,
917 0x021b001c, 0x04008040,
918 0x021b0020, 0x00005800,
919 0x021b0818, 0x00011117,
920 0x021b4818, 0x00011117,
921 0x021b0004, 0x0002556D,
922 0x021b0404, 0x00011006,
923 0x021b001c, 0x00000000,
924};
925
926static void ddr_init(int *table, int size)
927{
928 int i;
929
930 for (i = 0; i < size / 2 ; i++)
931 writel(table[2 * i + 1], table[2 * i]);
932}
933
934static void spl_dram_init(void)
935{
936 if (is_mx6dq())
937 ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
938 else if (is_mx6dqp())
939 ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
940 else if (is_mx6sdl())
941 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
942}
943
944void board_init_f(ulong dummy)
945{
946
947 spl_dram_init();
948
949
950 arch_cpu_init();
951
952 ccgr_init();
953 gpr_init();
954
955
956 board_early_init_f();
957
958
959 timer_init();
960
961
962 preloader_console_init();
963
964
965 memset(__bss_start, 0, __bss_end - __bss_start);
966
967
968 board_init_r(NULL, 0);
969}
970#endif
971
972#ifdef CONFIG_SPL_LOAD_FIT
973int board_fit_config_name_match(const char *name)
974{
975 if (is_mx6dq()) {
976 if (!strcmp(name, "imx6q-sabresd"))
977 return 0;
978 } else if (is_mx6dqp()) {
979 if (!strcmp(name, "imx6qp-sabresd"))
980 return 0;
981 } else if (is_mx6dl()) {
982 if (!strcmp(name, "imx6dl-sabresd"))
983 return 0;
984 }
985
986 return -1;
987}
988#endif
989
