LXR uboot/board/freescale/t102xrdb/ddr.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2014 Freescale Semiconductor, Inc.
   4 */
   5
   6#include <common.h>
   7#include <i2c.h>
   8#include <hwconfig.h>
   9#include <asm/mmu.h>
  10#include <fsl_ddr_sdram.h>
  11#include <fsl_ddr_dimm_params.h>
  12#include <asm/fsl_law.h>
  13#include <asm/mpc85xx_gpio.h>
  14
  15DECLARE_GLOBAL_DATA_PTR;
  16
  17struct board_specific_parameters {
  18        u32 n_ranks;
  19        u32 datarate_mhz_high;
  20        u32 rank_gb;
  21        u32 clk_adjust;
  22        u32 wrlvl_start;
  23        u32 wrlvl_ctl_2;
  24        u32 wrlvl_ctl_3;
  25};
  26
  27/*
  28 * datarate_mhz_high values need to be in ascending order
  29 */
  30static const struct board_specific_parameters udimm0[] = {
  31        /*
  32         * memory controller 0
  33         *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
  34         * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
  35         */
  36        {2,  833,   0,  8,  6,  0x06060607,  0x08080807,},
  37        {2,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
  38        {2,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
  39        {1,  833,   0,  8,  6,  0x06060607,  0x08080807,},
  40        {1,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
  41        {1,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
  42        {}
  43};
  44
  45static const struct board_specific_parameters *udimms[] = {
  46        udimm0,
  47};
  48
  49void fsl_ddr_board_options(memctl_options_t *popts,
  50                           dimm_params_t *pdimm,
  51                           unsigned int ctrl_num)
  52{
  53        const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  54        ulong ddr_freq;
  55        struct cpu_type *cpu = gd->arch.cpu;
  56
  57        if (ctrl_num > 1) {
  58                printf("Not supported controller number %d\n", ctrl_num);
  59                return;
  60        }
  61        if (!pdimm->n_ranks)
  62                return;
  63
  64        pbsp = udimms[0];
  65
  66        /* Get clk_adjust according to the board ddr freqency and n_banks
  67         * specified in board_specific_parameters table.
  68         */
  69        ddr_freq = get_ddr_freq(0) / 1000000;
  70        while (pbsp->datarate_mhz_high) {
  71                if (pbsp->n_ranks == pdimm->n_ranks &&
  72                    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
  73                        if (ddr_freq <= pbsp->datarate_mhz_high) {
  74                                popts->clk_adjust = pbsp->clk_adjust;
  75                                popts->wrlvl_start = pbsp->wrlvl_start;
  76                                popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  77                                popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  78                                goto found;
  79                        }
  80                        pbsp_highest = pbsp;
  81                }
  82                pbsp++;
  83        }
  84
  85        if (pbsp_highest) {
  86                printf("Error: board specific timing not found\n");
  87                printf("for data rate %lu MT/s\n", ddr_freq);
  88                printf("Trying to use the highest speed (%u) parameters\n",
  89                       pbsp_highest->datarate_mhz_high);
  90                popts->clk_adjust = pbsp_highest->clk_adjust;
  91                popts->wrlvl_start = pbsp_highest->wrlvl_start;
  92                popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  93                popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  94        } else {
  95                panic("DIMM is not supported by this board");
  96        }
  97found:
  98        debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
  99              pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
 100        debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ",
 101              pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2);
 102        debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3);
 103
 104        /*
 105         * Factors to consider for half-strength driver enable:
 106         *      - number of DIMMs installed
 107         */
 108        popts->half_strength_driver_enable = 0;
 109        /*
 110         * Write leveling override
 111         */
 112        popts->wrlvl_override = 1;
 113        popts->wrlvl_sample = 0xf;
 114
 115        /*
 116         * rtt and rtt_wr override
 117         */
 118        popts->rtt_override = 0;
 119
 120        /* Enable ZQ calibration */
 121        popts->zq_en = 1;
 122
 123        /* DHC_EN =1, ODT = 75 Ohm */
 124        popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF);
 125        popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF);
 126
 127        /* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit,
 128         * force DDR bus width to 32bit for T1023
 129         */
 130        if (cpu->soc_ver == SVR_T1023)
 131                popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
 132
 133#ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
 134        /* for DDR bus 32bit test on T1024 */
 135        popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
 136#endif
 137
 138#ifdef CONFIG_TARGET_T1023RDB
 139        popts->wrlvl_ctl_2 = 0x07070606;
 140        popts->half_strength_driver_enable = 1;
 141        popts->cpo_sample = 0x43;
 142#elif defined(CONFIG_TARGET_T1024RDB)
 143        /* optimize cpo for erratum A-009942 */
 144        popts->cpo_sample = 0x52;
 145#endif
 146}
 147
 148#ifdef CONFIG_SYS_DDR_RAW_TIMING
 149/* 2GB discrete DDR4 MT40A512M8HX on T1023RDB */
 150dimm_params_t ddr_raw_timing = {
 151        .n_ranks = 1,
 152        .rank_density = 0x80000000,
 153        .capacity = 0x80000000,
 154        .primary_sdram_width = 32,
 155        .ec_sdram_width = 8,
 156        .registered_dimm = 0,
 157        .mirrored_dimm = 0,
 158        .n_row_addr = 15,
 159        .n_col_addr = 10,
 160        .bank_addr_bits = 2,
 161        .bank_group_bits = 2,
 162        .edc_config = 0,
 163        .burst_lengths_bitmask = 0x0c,
 164        .tckmin_x_ps = 938,
 165        .tckmax_ps = 1500,
 166        .caslat_x = 0x000DFA00,
 167        .taa_ps = 13500,
 168        .trcd_ps = 13500,
 169        .trp_ps = 13500,
 170        .tras_ps = 33000,
 171        .trc_ps = 46500,
 172        .trfc1_ps = 260000,
 173        .trfc2_ps = 160000,
 174        .trfc4_ps = 110000,
 175        .tfaw_ps = 25000,
 176        .trrds_ps = 3700,
 177        .trrdl_ps = 5300,
 178        .tccdl_ps = 5355,
 179        .refresh_rate_ps = 7800000,
 180        .dq_mapping[0] = 0x0,
 181        .dq_mapping[1] = 0x0,
 182        .dq_mapping[2] = 0x0,
 183        .dq_mapping[3] = 0x0,
 184        .dq_mapping[4] = 0x0,
 185        .dq_mapping[5] = 0x0,
 186        .dq_mapping[6] = 0x0,
 187        .dq_mapping[7] = 0x0,
 188        .dq_mapping[8] = 0x0,
 189        .dq_mapping[9] = 0x0,
 190        .dq_mapping[10] = 0x0,
 191        .dq_mapping[11] = 0x0,
 192        .dq_mapping[12] = 0x0,
 193        .dq_mapping[13] = 0x0,
 194        .dq_mapping[14] = 0x0,
 195        .dq_mapping[15] = 0x0,
 196        .dq_mapping[16] = 0x0,
 197        .dq_mapping[17] = 0x0,
 198        .dq_mapping_ors = 1,
 199};
 200
 201int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 202                unsigned int controller_number,
 203                unsigned int dimm_number)
 204{
 205        const char dimm_model[] = "Fixed DDR4 on board";
 206
 207        if (((controller_number == 0) && (dimm_number == 0)) ||
 208            ((controller_number == 1) && (dimm_number == 0))) {
 209                memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
 210                memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
 211                memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
 212        }
 213
 214        return 0;
 215}
 216#endif
 217
 218#if defined(CONFIG_DEEP_SLEEP)
 219void board_mem_sleep_setup(void)
 220{
 221        void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
 222
 223        /* does not provide HW signals for power management */
 224        clrbits_8(cpld_base + 0x17, 0x40);
 225        /* Disable MCKE isolation */
 226        gpio_set_value(2, 0);
 227        udelay(1);
 228}
 229#endif
 230
 231int dram_init(void)
 232{
 233        phys_size_t dram_size;
 234
 235#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 236#ifndef CONFIG_SYS_DDR_RAW_TIMING
 237        puts("Initializing....using SPD\n");
 238#endif
 239        dram_size = fsl_ddr_sdram();
 240#else
 241        /* DDR has been initialised by first stage boot loader */
 242        dram_size =  fsl_ddr_sdram_size();
 243#endif
 244        dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 245        dram_size *= 0x100000;
 246
 247#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 248        fsl_dp_resume();
 249#endif
 250
 251        gd->ram_size = dram_size;
 252
 253        return 0;
 254}
 255