LXR uboot/board/mscc/ocelot/ocelot.c

   1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2/*
   3 * Copyright (c) 2018 Microsemi Corporation
   4 */
   5
   6#include <common.h>
   7#include <init.h>
   8#include <asm/io.h>
   9#include <asm/addrspace.h>
  10#include <asm/types.h>
  11#include <spi.h>
  12#include <led.h>
  13#include <wait_bit.h>
  14#include <miiphy.h>
  15
  16DECLARE_GLOBAL_DATA_PTR;
  17
  18enum {
  19        BOARD_TYPE_PCB120 = 0xAABBCC00,
  20        BOARD_TYPE_PCB123,
  21};
  22
  23void mscc_switch_reset(bool enter)
  24{
  25        /* Nasty workaround to avoid GPIO19 (DDR!) being reset */
  26        mscc_gpio_set_alternate(19, 2);
  27
  28        debug("applying SwC reset\n");
  29
  30        writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
  31        writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
  32
  33        if (wait_for_bit_le32(BASE_DEVCPU_GCB + PERF_SOFT_RST,
  34                              PERF_SOFT_RST_SOFT_CHIP_RST, false, 5000, false))
  35                pr_err("Tiemout while waiting for switch reset\n");
  36
  37        /*
  38         * Reset GPIO19 mode back as regular GPIO, output, high (DDR
  39         * not reset) (Order is important)
  40         */
  41        setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
  42        writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET);
  43        mscc_gpio_set_alternate(19, 0);
  44}
  45
  46int board_phy_config(struct phy_device *phydev)
  47{
  48        if (gd->board_type == BOARD_TYPE_PCB123)
  49                return 0;
  50
  51        phy_write(phydev, 0, 31, 0x10);
  52        phy_write(phydev, 0, 18, 0x80F0);
  53        while (phy_read(phydev, 0, 18) & 0x8000)
  54                ;
  55        phy_write(phydev, 0, 31, 0);
  56
  57        return 0;
  58}
  59
  60void board_debug_uart_init(void)
  61{
  62        /* too early for the pinctrl driver, so configure the UART pins here */
  63        mscc_gpio_set_alternate(6, 1);
  64        mscc_gpio_set_alternate(7, 1);
  65}
  66
  67int board_early_init_r(void)
  68{
  69        /* Prepare SPI controller to be used in master mode */
  70        writel(0, BASE_CFG + ICPU_SW_MODE);
  71        clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
  72                        ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
  73                        ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
  74
  75        /* Address of boot parameters */
  76        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
  77
  78        /* LED setup */
  79        if (IS_ENABLED(CONFIG_LED))
  80                led_default_state();
  81
  82        return 0;
  83}
  84
  85static void do_board_detect(void)
  86{
  87        u16 dummy = 0;
  88
  89        /* Enable MIIM */
  90        mscc_gpio_set_alternate(14, 1);
  91        mscc_gpio_set_alternate(15, 1);
  92        if (mscc_phy_rd(1, 0, 0, &dummy) == 0)
  93                gd->board_type = BOARD_TYPE_PCB120;
  94        else
  95                gd->board_type = BOARD_TYPE_PCB123;
  96}
  97
  98#if defined(CONFIG_MULTI_DTB_FIT)
  99int board_fit_config_name_match(const char *name)
 100{
 101        if (gd->board_type == BOARD_TYPE_PCB120 &&
 102            strcmp(name, "ocelot_pcb120") == 0)
 103                return 0;
 104
 105        if (gd->board_type == BOARD_TYPE_PCB123 &&
 106            strcmp(name, "ocelot_pcb123") == 0)
 107                return 0;
 108
 109        return -1;
 110}
 111#endif
 112
 113#if defined(CONFIG_DTB_RESELECT)
 114int embedded_dtb_select(void)
 115{
 116        do_board_detect();
 117        fdtdec_setup();
 118
 119        return 0;
 120}
 121#endif
 122