LXR uboot/board/renesas/koelsch/koelsch.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * board/renesas/koelsch/koelsch.c
   4 *
   5 * Copyright (C) 2013 Renesas Electronics Corporation
   6 *
   7 */
   8
   9#include <common.h>
  10#include <env.h>
  11#include <malloc.h>
  12#include <dm.h>
  13#include <dm/platform_data/serial_sh.h>
  14#include <env_internal.h>
  15#include <asm/processor.h>
  16#include <asm/mach-types.h>
  17#include <asm/io.h>
  18#include <linux/errno.h>
  19#include <asm/arch/sys_proto.h>
  20#include <asm/gpio.h>
  21#include <asm/arch/rmobile.h>
  22#include <asm/arch/rcar-mstp.h>
  23#include <asm/arch/sh_sdhi.h>
  24#include <netdev.h>
  25#include <miiphy.h>
  26#include <i2c.h>
  27#include <div64.h>
  28#include "qos.h"
  29
  30DECLARE_GLOBAL_DATA_PTR;
  31
  32#define CLK2MHZ(clk)    (clk / 1000 / 1000)
  33void s_init(void)
  34{
  35        struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
  36        struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
  37        u32 stc;
  38
  39        /* Watchdog init */
  40        writel(0xA5A5A500, &rwdt->rwtcsra);
  41        writel(0xA5A5A500, &swdt->swtcsra);
  42
  43        /* CPU frequency setting. Set to 1.5GHz */
  44        stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
  45        clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
  46
  47        /* QoS */
  48        qos_init();
  49}
  50
  51#define TMU0_MSTP125    BIT(25)
  52
  53#define SD1CKCR         0xE6150078
  54#define SD2CKCR         0xE615026C
  55#define SD_97500KHZ     0x7
  56
  57int board_early_init_f(void)
  58{
  59        mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
  60
  61        /*
  62         * SD0 clock is set to 97.5MHz by default.
  63         * Set SD1 and SD2 to the 97.5MHz as well.
  64         */
  65        writel(SD_97500KHZ, SD1CKCR);
  66        writel(SD_97500KHZ, SD2CKCR);
  67
  68        return 0;
  69}
  70
  71#define ETHERNET_PHY_RESET      176     /* GPIO 5 22 */
  72
  73int board_init(void)
  74{
  75        /* adress of boot parameters */
  76        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  77
  78        /* Force ethernet PHY out of reset */
  79        gpio_request(ETHERNET_PHY_RESET, "phy_reset");
  80        gpio_direction_output(ETHERNET_PHY_RESET, 0);
  81        mdelay(10);
  82        gpio_direction_output(ETHERNET_PHY_RESET, 1);
  83
  84        return 0;
  85}
  86
  87int dram_init(void)
  88{
  89        if (fdtdec_setup_mem_size_base() != 0)
  90                return -EINVAL;
  91
  92        return 0;
  93}
  94
  95int dram_init_banksize(void)
  96{
  97        fdtdec_setup_memory_banksize();
  98
  99        return 0;
 100}
 101
 102/* Koelsch has KSZ8041NL/RNL */
 103#define PHY_CONTROL1            0x1E
 104#define PHY_LED_MODE            0xC000
 105#define PHY_LED_MODE_ACK        0x4000
 106int board_phy_config(struct phy_device *phydev)
 107{
 108        int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
 109        ret &= ~PHY_LED_MODE;
 110        ret |= PHY_LED_MODE_ACK;
 111        ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
 112
 113        return 0;
 114}
 115
 116void reset_cpu(ulong addr)
 117{
 118        struct udevice *dev;
 119        const u8 pmic_bus = 6;
 120        const u8 pmic_addr = 0x58;
 121        u8 data;
 122        int ret;
 123
 124        ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
 125        if (ret)
 126                hang();
 127
 128        ret = dm_i2c_read(dev, 0x13, &data, 1);
 129        if (ret)
 130                hang();
 131
 132        data |= BIT(1);
 133
 134        ret = dm_i2c_write(dev, 0x13, &data, 1);
 135        if (ret)
 136                hang();
 137}
 138
 139enum env_location env_get_location(enum env_operation op, int prio)
 140{
 141        const u32 load_magic = 0xb33fc0de;
 142
 143        /* Block environment access if loaded using JTAG */
 144        if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
 145            (op != ENVOP_INIT))
 146                return ENVL_UNKNOWN;
 147
 148        if (prio)
 149                return ENVL_UNKNOWN;
 150
 151        return ENVL_SPI_FLASH;
 152}
 153