LXR uboot/board/ronetix/pm9261/pm9261.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2007-2008
   4 * Stelian Pop <stelian@popies.net>
   5 * Lead Tech Design <www.leadtechdesign.com>
   6 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
   7 * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   8 */
   9
  10#include <common.h>
  11#include <vsprintf.h>
  12#include <linux/sizes.h>
  13#include <asm/io.h>
  14#include <asm/gpio.h>
  15#include <asm/arch/at91sam9_smc.h>
  16#include <asm/arch/at91_common.h>
  17#include <asm/arch/at91_rstc.h>
  18#include <asm/arch/at91_matrix.h>
  19#include <asm/arch/clk.h>
  20#include <asm/arch/gpio.h>
  21#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
  22#include <net.h>
  23#endif
  24#include <netdev.h>
  25#include <asm/mach-types.h>
  26
  27DECLARE_GLOBAL_DATA_PTR;
  28
  29/* ------------------------------------------------------------------------- */
  30/*
  31 * Miscelaneous platform dependent initialisations
  32 */
  33
  34#ifdef CONFIG_CMD_NAND
  35static void pm9261_nand_hw_init(void)
  36{
  37        unsigned long csa;
  38        struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  39        struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  40
  41        /* Enable CS3 */
  42        csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
  43        writel(csa, &matrix->csa);
  44
  45        /* Configure SMC CS3 for NAND/SmartMedia */
  46        writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  47                AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  48                &smc->cs[3].setup);
  49
  50        writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  51                AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  52                &smc->cs[3].pulse);
  53
  54        writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  55                &smc->cs[3].cycle);
  56
  57        writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  58                AT91_SMC_MODE_EXNW_DISABLE |
  59#ifdef CONFIG_SYS_NAND_DBW_16
  60                AT91_SMC_MODE_DBW_16 |
  61#else /* CONFIG_SYS_NAND_DBW_8 */
  62                AT91_SMC_MODE_DBW_8 |
  63#endif
  64                AT91_SMC_MODE_TDF_CYCLE(2),
  65                &smc->cs[3].mode);
  66
  67        at91_periph_clk_enable(ATMEL_ID_PIOA);
  68        at91_periph_clk_enable(ATMEL_ID_PIOC);
  69
  70        /* Configure RDY/BSY */
  71        gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
  72
  73        /* Enable NandFlash */
  74        gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  75
  76        at91_set_a_periph(AT91_PIO_PORTC, 0, 0);        /* NANDOE */
  77        at91_set_a_periph(AT91_PIO_PORTC, 1, 0);        /* NANDWE */
  78}
  79#endif
  80
  81
  82#ifdef CONFIG_DRIVER_DM9000
  83static void pm9261_dm9000_hw_init(void)
  84{
  85        struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  86
  87        /* Configure SMC CS2 for DM9000 */
  88        writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
  89                AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
  90                &smc->cs[2].setup);
  91
  92        writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
  93                AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
  94                &smc->cs[2].pulse);
  95
  96        writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
  97                &smc->cs[2].cycle);
  98
  99        writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
 100                AT91_SMC_MODE_EXNW_DISABLE |
 101                AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
 102                AT91_SMC_MODE_TDF_CYCLE(1),
 103                &smc->cs[2].mode);
 104
 105        /* Configure Interrupt pin as input, no pull-up */
 106        at91_periph_clk_enable(ATMEL_ID_PIOA);
 107        at91_set_pio_input(AT91_PIO_PORTA, 24, 0);
 108}
 109#endif
 110
 111int board_early_init_f(void)
 112{
 113        return 0;
 114}
 115
 116int board_init(void)
 117{
 118        /* arch number of PM9261-Board */
 119        gd->bd->bi_arch_number = MACH_TYPE_PM9261;
 120
 121        /* adress of boot parameters */
 122        gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 123
 124#ifdef CONFIG_CMD_NAND
 125        pm9261_nand_hw_init();
 126#endif
 127#ifdef CONFIG_DRIVER_DM9000
 128        pm9261_dm9000_hw_init();
 129#endif
 130        return 0;
 131}
 132
 133#ifdef CONFIG_DRIVER_DM9000
 134int board_eth_init(bd_t *bis)
 135{
 136        return dm9000_initialize(bis);
 137}
 138#endif
 139
 140int dram_init(void)
 141{
 142        /* dram_init must store complete ramsize in gd->ram_size */
 143        gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
 144                                PHYS_SDRAM_SIZE);
 145        return 0;
 146}
 147
 148int dram_init_banksize(void)
 149{
 150        gd->bd->bi_dram[0].start = PHYS_SDRAM;
 151        gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 152
 153        return 0;
 154}
 155
 156#ifdef CONFIG_RESET_PHY_R
 157void reset_phy(void)
 158{
 159#ifdef CONFIG_DRIVER_DM9000
 160        /*
 161         * Initialize ethernet HW addr prior to starting Linux,
 162         * needed for nfsroot
 163         */
 164        eth_init();
 165#endif
 166}
 167#endif
 168
 169#ifdef CONFIG_DISPLAY_BOARDINFO
 170int checkboard (void)
 171{
 172        char buf[32];
 173
 174        printf ("Board : Ronetix PM9261\n");
 175        printf ("Crystal frequency: %8s MHz\n",
 176                                        strmhz(buf, get_main_clk_rate()));
 177        printf ("CPU clock        : %8s MHz\n",
 178                                        strmhz(buf, get_cpu_clk_rate()));
 179        printf ("Master clock     : %8s MHz\n",
 180                                        strmhz(buf, get_mck_clk_rate()));
 181
 182        return 0;
 183}
 184#endif
 185