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16#include <common.h>
17#include <dm.h>
18#include <dm/platform_data/spi_coldfire.h>
19#include <spi.h>
20#include <malloc.h>
21#include <asm/coldfire/dspi.h>
22#include <asm/io.h>
23
24struct coldfire_spi_priv {
25 struct dspi *regs;
26 uint baudrate;
27 int mode;
28 int charbit;
29};
30
31DECLARE_GLOBAL_DATA_PTR;
32
33#ifndef CONFIG_SPI_IDLE_VAL
34#if defined(CONFIG_SPI_MMC)
35#define CONFIG_SPI_IDLE_VAL 0xFFFF
36#else
37#define CONFIG_SPI_IDLE_VAL 0x0
38#endif
39#endif
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55#define SPI_MODE_MOD 0x00200000
56#define SPI_MODE_DBLRATE 0x00100000
57
58#define SPI_MODE_XFER_SZ_MASK 0xf0000000
59#define SPI_MODE_DLY_PRE_MASK 0x0fc00000
60#define SPI_MODE_DLY_SCA_MASK 0x000fff00
61
62#define MCF_FRM_SZ_16BIT DSPI_CTAR_TRSZ(0xf)
63#define MCF_DSPI_SPEED_BESTMATCH 0x7FFFFFFF
64#define MCF_DSPI_MAX_CTAR_REGS 8
65
66
67#define MCF_DSPI_DEFAULT_SCK_FREQ 10000000
68#define MCF_DSPI_DEFAULT_MAX_CS 4
69#define MCF_DSPI_DEFAULT_MODE 0
70
71#define MCF_DSPI_DEFAULT_CTAR (DSPI_CTAR_TRSZ(7) | \
72 DSPI_CTAR_PCSSCK_1CLK | \
73 DSPI_CTAR_PASC(0) | \
74 DSPI_CTAR_PDT(0) | \
75 DSPI_CTAR_CSSCK(0) | \
76 DSPI_CTAR_ASC(0) | \
77 DSPI_CTAR_DT(1) | \
78 DSPI_CTAR_BR(6))
79
80#define MCF_CTAR_MODE_MASK (MCF_FRM_SZ_16BIT | \
81 DSPI_CTAR_PCSSCK(3) | \
82 DSPI_CTAR_PASC_7CLK | \
83 DSPI_CTAR_PDT(3) | \
84 DSPI_CTAR_CSSCK(0x0f) | \
85 DSPI_CTAR_ASC(0x0f) | \
86 DSPI_CTAR_DT(0x0f))
87
88#define setup_ctrl(ctrl, cs) ((ctrl & 0xFF000000) | ((1 << cs) << 16))
89
90static inline void cfspi_tx(struct coldfire_spi_priv *cfspi,
91 u32 ctrl, u16 data)
92{
93
94
95
96 while ((readl(&cfspi->regs->sr) & 0x0000F000) >= 0x4000)
97 ;
98
99 writel(ctrl | data, &cfspi->regs->tfr);
100}
101
102static inline u16 cfspi_rx(struct coldfire_spi_priv *cfspi)
103{
104
105 while ((readl(&cfspi->regs->sr) & 0x000000F0) == 0)
106 ;
107
108 return readw(&cfspi->regs->rfr);
109}
110
111static int coldfire_spi_claim_bus(struct udevice *dev)
112{
113 struct udevice *bus = dev->parent;
114 struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
115 struct dspi *dspi = cfspi->regs;
116 struct dm_spi_slave_platdata *slave_plat =
117 dev_get_parent_platdata(dev);
118
119 if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
120 return -1;
121
122
123 clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
124
125 dspi_chip_select(slave_plat->cs);
126
127 return 0;
128}
129
130static int coldfire_spi_release_bus(struct udevice *dev)
131{
132 struct udevice *bus = dev->parent;
133 struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
134 struct dspi *dspi = cfspi->regs;
135 struct dm_spi_slave_platdata *slave_plat =
136 dev_get_parent_platdata(dev);
137
138
139 clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
140
141 dspi_chip_unselect(slave_plat->cs);
142
143 return 0;
144}
145
146static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen,
147 const void *dout, void *din,
148 unsigned long flags)
149{
150 struct udevice *bus = dev_get_parent(dev);
151 struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
152 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
153 u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
154 u8 *spi_rd = NULL, *spi_wr = NULL;
155 static u32 ctrl;
156 uint len = bitlen >> 3;
157
158 if (cfspi->charbit == 16) {
159 bitlen >>= 1;
160 spi_wr16 = (u16 *)dout;
161 spi_rd16 = (u16 *)din;
162 } else {
163 spi_wr = (u8 *)dout;
164 spi_rd = (u8 *)din;
165 }
166
167 if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
168 ctrl |= DSPI_TFR_CONT;
169
170 ctrl = setup_ctrl(ctrl, slave_plat->cs);
171
172 if (len > 1) {
173 int tmp_len = len - 1;
174
175 while (tmp_len--) {
176 if (dout) {
177 if (cfspi->charbit == 16)
178 cfspi_tx(cfspi, ctrl, *spi_wr16++);
179 else
180 cfspi_tx(cfspi, ctrl, *spi_wr++);
181 cfspi_rx(cfspi);
182 }
183
184 if (din) {
185 cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
186 if (cfspi->charbit == 16)
187 *spi_rd16++ = cfspi_rx(cfspi);
188 else
189 *spi_rd++ = cfspi_rx(cfspi);
190 }
191 }
192
193 len = 1;
194 }
195
196 if (flags & SPI_XFER_END)
197 ctrl &= ~DSPI_TFR_CONT;
198
199 if (len) {
200 if (dout) {
201 if (cfspi->charbit == 16)
202 cfspi_tx(cfspi, ctrl, *spi_wr16);
203 else
204 cfspi_tx(cfspi, ctrl, *spi_wr);
205 cfspi_rx(cfspi);
206 }
207
208 if (din) {
209 cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
210 if (cfspi->charbit == 16)
211 *spi_rd16 = cfspi_rx(cfspi);
212 else
213 *spi_rd = cfspi_rx(cfspi);
214 }
215 } else {
216
217 cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
218 cfspi_rx(cfspi);
219 }
220
221 return 0;
222}
223
224static int coldfire_spi_set_speed(struct udevice *bus, uint max_hz)
225{
226 struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
227 struct dspi *dspi = cfspi->regs;
228 int prescaler[] = { 2, 3, 5, 7 };
229 int scaler[] = {
230 2, 4, 6, 8,
231 16, 32, 64, 128,
232 256, 512, 1024, 2048,
233 4096, 8192, 16384, 32768
234 };
235 int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0;
236 int best_i, best_j, bestmatch = MCF_DSPI_SPEED_BESTMATCH, baud_speed;
237 u32 bus_setup;
238
239 cfspi->baudrate = max_hz;
240
241
242 bus_setup = readl(&dspi->ctar[bus->seq]);
243
244 tmp = (prescaler[3] * scaler[15]);
245
246 if ((cfspi->baudrate > (gd->bus_clk >> 1)) ||
247 (cfspi->baudrate < (gd->bus_clk / tmp))) {
248 printf("Exceed baudrate limitation: Max %d - Min %d\n",
249 (int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp));
250 return -1;
251 }
252
253
254 if ((bus_setup & DSPI_CTAR_DBR) ||
255 (cfspi->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
256 bus_setup |= DSPI_CTAR_DBR;
257 dbr = 1;
258 }
259
260
261 if (cfspi->mode & SPI_MODE_MOD) {
262
263
264
265
266 if (cfspi->mode & SPI_MODE_DBLRATE) {
267 bus_setup |= DSPI_CTAR_DBR;
268 dbr = 1;
269 }
270 }
271
272 pbrcnt = sizeof(prescaler) / sizeof(int);
273 brcnt = sizeof(scaler) / sizeof(int);
274
275
276 for (best_i = 0, best_j = 0, i = 0; i < pbrcnt; i++) {
277 baud_speed = gd->bus_clk / prescaler[i];
278 for (j = 0; j < brcnt; j++) {
279 tmp = (baud_speed / scaler[j]) * (1 + dbr);
280
281 if (tmp > cfspi->baudrate)
282 diff = tmp - cfspi->baudrate;
283 else
284 diff = cfspi->baudrate - tmp;
285
286 if (diff < bestmatch) {
287 bestmatch = diff;
288 best_i = i;
289 best_j = j;
290 }
291 }
292 }
293
294 bus_setup &= ~(DSPI_CTAR_PBR(0x03) | DSPI_CTAR_BR(0x0f));
295 bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
296 writel(bus_setup, &dspi->ctar[bus->seq]);
297
298 return 0;
299}
300
301static int coldfire_spi_set_mode(struct udevice *bus, uint mode)
302{
303 struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
304 struct dspi *dspi = cfspi->regs;
305 u32 bus_setup = 0;
306
307 cfspi->mode = mode;
308
309 if (cfspi->mode & SPI_CPOL)
310 bus_setup |= DSPI_CTAR_CPOL;
311 if (cfspi->mode & SPI_CPHA)
312 bus_setup |= DSPI_CTAR_CPHA;
313 if (cfspi->mode & SPI_LSB_FIRST)
314 bus_setup |= DSPI_CTAR_LSBFE;
315
316
317 if (cfspi->mode & SPI_MODE_MOD) {
318 if ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) == 0)
319 bus_setup |=
320 readl(&dspi->ctar[bus->seq]) & MCF_FRM_SZ_16BIT;
321 else
322 bus_setup |=
323 ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) >> 1);
324
325
326 bus_setup |= (cfspi->mode & SPI_MODE_DLY_PRE_MASK) >> 4;
327
328 bus_setup |= (cfspi->mode & SPI_MODE_DLY_SCA_MASK) >> 4;
329 } else {
330 bus_setup |=
331 (readl(&dspi->ctar[bus->seq]) & MCF_CTAR_MODE_MASK);
332 }
333
334 cfspi->charbit =
335 ((readl(&dspi->ctar[bus->seq]) & MCF_FRM_SZ_16BIT) ==
336 MCF_FRM_SZ_16BIT) ? 16 : 8;
337
338 setbits_be32(&dspi->ctar[bus->seq], bus_setup);
339
340 return 0;
341}
342
343static int coldfire_spi_probe(struct udevice *bus)
344{
345 struct coldfire_spi_platdata *plat = dev_get_platdata(bus);
346 struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
347 struct dspi *dspi = cfspi->regs;
348 int i;
349
350 cfspi->regs = (struct dspi *)plat->regs_addr;
351
352 cfspi->baudrate = plat->speed_hz;
353 cfspi->mode = plat->mode;
354
355 for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++) {
356 unsigned int ctar = 0;
357
358 if (plat->ctar[i][0] == 0)
359 break;
360
361 ctar = DSPI_CTAR_TRSZ(plat->ctar[i][0]) |
362 DSPI_CTAR_PCSSCK(plat->ctar[i][1]) |
363 DSPI_CTAR_PASC(plat->ctar[i][2]) |
364 DSPI_CTAR_PDT(plat->ctar[i][3]) |
365 DSPI_CTAR_CSSCK(plat->ctar[i][4]) |
366 DSPI_CTAR_ASC(plat->ctar[i][5]) |
367 DSPI_CTAR_DT(plat->ctar[i][6]) |
368 DSPI_CTAR_BR(plat->ctar[i][7]);
369
370 writel(ctar, &cfspi->regs->ctar[i]);
371 }
372
373
374 for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++)
375 writel(MCF_DSPI_DEFAULT_CTAR, &dspi->ctar[i]);
376
377 dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 |
378 DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 |
379 DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 |
380 DSPI_MCR_CRXF | DSPI_MCR_CTXF;
381
382 return 0;
383}
384
385void spi_init(void)
386{
387}
388
389#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
390static int coldfire_dspi_ofdata_to_platdata(struct udevice *bus)
391{
392 fdt_addr_t addr;
393 struct coldfire_spi_platdata *plat = bus->platdata;
394 const void *blob = gd->fdt_blob;
395 int node = dev_of_offset(bus);
396 int *ctar, len;
397
398 addr = devfdt_get_addr(bus);
399 if (addr == FDT_ADDR_T_NONE)
400 return -ENOMEM;
401
402 plat->regs_addr = addr;
403
404 plat->num_cs = fdtdec_get_int(blob, node, "num-cs",
405 MCF_DSPI_DEFAULT_MAX_CS);
406
407 plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
408 MCF_DSPI_DEFAULT_SCK_FREQ);
409
410 plat->mode = fdtdec_get_int(blob, node, "spi-mode",
411 MCF_DSPI_DEFAULT_MODE);
412
413 memset(plat->ctar, 0, sizeof(plat->ctar));
414
415 ctar = (int *)fdt_getprop(blob, node, "ctar-params", &len);
416
417 if (ctar && len) {
418 int i, q, ctar_regs;
419
420 ctar_regs = len / sizeof(unsigned int) / MAX_CTAR_FIELDS;
421
422 if (ctar_regs > MAX_CTAR_REGS)
423 ctar_regs = MAX_CTAR_REGS;
424
425 for (i = 0; i < ctar_regs; i++) {
426 for (q = 0; q < MAX_CTAR_FIELDS; q++)
427 plat->ctar[i][q] = *ctar++;
428 }
429 }
430
431 debug("DSPI: regs=%pa, max-frequency=%d, num-cs=%d, mode=%d\n",
432 (void *)plat->regs_addr,
433 plat->speed_hz, plat->num_cs, plat->mode);
434
435 return 0;
436}
437
438static const struct udevice_id coldfire_spi_ids[] = {
439 { .compatible = "fsl,mcf-dspi" },
440 { }
441};
442#endif
443
444static const struct dm_spi_ops coldfire_spi_ops = {
445 .claim_bus = coldfire_spi_claim_bus,
446 .release_bus = coldfire_spi_release_bus,
447 .xfer = coldfire_spi_xfer,
448 .set_speed = coldfire_spi_set_speed,
449 .set_mode = coldfire_spi_set_mode,
450};
451
452U_BOOT_DRIVER(coldfire_spi) = {
453 .name = "spi_coldfire",
454 .id = UCLASS_SPI,
455#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
456 .of_match = coldfire_spi_ids,
457 .ofdata_to_platdata = coldfire_dspi_ofdata_to_platdata,
458 .platdata_auto_alloc_size = sizeof(struct coldfire_spi_platdata),
459#endif
460 .probe = coldfire_spi_probe,
461 .ops = &coldfire_spi_ops,
462 .priv_auto_alloc_size = sizeof(struct coldfire_spi_priv),
463};
464
