LXR uboot/drivers/spi/xilinx

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Xilinx SPI driver
   4 *
   5 * Supports 8 bit SPI transfers only, with or w/o FIFO
   6 *
   7 * Based on bfin_spi.c, by way of altera_spi.c
   8 * Copyright (c) 2015 Jagan Teki <jteki@openedev.com>
   9 * Copyright (c) 2012 Stephan Linz <linz@li-pro.net>
  10 * Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca>
  11 * Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw>
  12 * Copyright (c) 2005-2008 Analog Devices Inc.
  13 */
  14
  15#include <config.h>
  16#include <common.h>
  17#include <dm.h>
  18#include <errno.h>
  19#include <malloc.h>
  20#include <spi.h>
  21#include <asm/io.h>
  22#include <wait_bit.h>
  23
  24/*
  25 * [0]: http://www.xilinx.com/support/documentation
  26 *
  27 * Xilinx SPI Register Definitions
  28 * [1]: [0]/ip_documentation/xps_spi.pdf
  29 *      page 8, Register Descriptions
  30 * [2]: [0]/ip_documentation/axi_spi_ds742.pdf
  31 *      page 7, Register Overview Table
  32 */
  33
  34/* SPI Control Register (spicr), [1] p9, [2] p8 */
  35#define SPICR_LSB_FIRST         BIT(9)
  36#define SPICR_MASTER_INHIBIT    BIT(8)
  37#define SPICR_MANUAL_SS         BIT(7)
  38#define SPICR_RXFIFO_RESEST     BIT(6)
  39#define SPICR_TXFIFO_RESEST     BIT(5)
  40#define SPICR_CPHA              BIT(4)
  41#define SPICR_CPOL              BIT(3)
  42#define SPICR_MASTER_MODE       BIT(2)
  43#define SPICR_SPE               BIT(1)
  44#define SPICR_LOOP              BIT(0)
  45
  46/* SPI Status Register (spisr), [1] p11, [2] p10 */
  47#define SPISR_SLAVE_MODE_SELECT BIT(5)
  48#define SPISR_MODF              BIT(4)
  49#define SPISR_TX_FULL           BIT(3)
  50#define SPISR_TX_EMPTY          BIT(2)
  51#define SPISR_RX_FULL           BIT(1)
  52#define SPISR_RX_EMPTY          BIT(0)
  53
  54/* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */
  55#define SPIDTR_8BIT_MASK        GENMASK(7, 0)
  56#define SPIDTR_16BIT_MASK       GENMASK(15, 0)
  57#define SPIDTR_32BIT_MASK       GENMASK(31, 0)
  58
  59/* SPI Data Receive Register (spidrr), [1] p12, [2] p12 */
  60#define SPIDRR_8BIT_MASK        GENMASK(7, 0)
  61#define SPIDRR_16BIT_MASK       GENMASK(15, 0)
  62#define SPIDRR_32BIT_MASK       GENMASK(31, 0)
  63
  64/* SPI Slave Select Register (spissr), [1] p13, [2] p13 */
  65#define SPISSR_MASK(cs)         (1 << (cs))
  66#define SPISSR_ACT(cs)          ~SPISSR_MASK(cs)
  67#define SPISSR_OFF              ~0UL
  68
  69/* SPI Software Reset Register (ssr) */
  70#define SPISSR_RESET_VALUE      0x0a
  71
  72#define XILSPI_MAX_XFER_BITS    8
  73#define XILSPI_SPICR_DFLT_ON    (SPICR_MANUAL_SS | SPICR_MASTER_MODE | \
  74                                SPICR_SPE)
  75#define XILSPI_SPICR_DFLT_OFF   (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS)
  76
  77#ifndef CONFIG_XILINX_SPI_IDLE_VAL
  78#define CONFIG_XILINX_SPI_IDLE_VAL      GENMASK(7, 0)
  79#endif
  80
  81#define XILINX_SPISR_TIMEOUT    10000 /* in milliseconds */
  82
  83/* xilinx spi register set */
  84struct xilinx_spi_regs {
  85        u32 __space0__[7];
  86        u32 dgier;      /* Device Global Interrupt Enable Register (DGIER) */
  87        u32 ipisr;      /* IP Interrupt Status Register (IPISR) */
  88        u32 __space1__;
  89        u32 ipier;      /* IP Interrupt Enable Register (IPIER) */
  90        u32 __space2__[5];
  91        u32 srr;        /* Softare Reset Register (SRR) */
  92        u32 __space3__[7];
  93        u32 spicr;      /* SPI Control Register (SPICR) */
  94        u32 spisr;      /* SPI Status Register (SPISR) */
  95        u32 spidtr;     /* SPI Data Transmit Register (SPIDTR) */
  96        u32 spidrr;     /* SPI Data Receive Register (SPIDRR) */
  97        u32 spissr;     /* SPI Slave Select Register (SPISSR) */
  98        u32 spitfor;    /* SPI Transmit FIFO Occupancy Register (SPITFOR) */
  99        u32 spirfor;    /* SPI Receive FIFO Occupancy Register (SPIRFOR) */
 100};
 101
 102/* xilinx spi priv */
 103struct xilinx_spi_priv {
 104        struct xilinx_spi_regs *regs;
 105        unsigned int freq;
 106        unsigned int mode;
 107        unsigned int fifo_depth;
 108        u8 startup;
 109};
 110
 111static int xilinx_spi_probe(struct udevice *bus)
 112{
 113        struct xilinx_spi_priv *priv = dev_get_priv(bus);
 114        struct xilinx_spi_regs *regs = priv->regs;
 115
 116        priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus);
 117
 118        priv->fifo_depth = dev_read_u32_default(bus, "fifo-size", 0);
 119
 120        writel(SPISSR_RESET_VALUE, &regs->srr);
 121
 122        return 0;
 123}
 124
 125static void spi_cs_activate(struct udevice *dev, uint cs)
 126{
 127        struct udevice *bus = dev_get_parent(dev);
 128        struct xilinx_spi_priv *priv = dev_get_priv(bus);
 129        struct xilinx_spi_regs *regs = priv->regs;
 130
 131        writel(SPISSR_ACT(cs), &regs->spissr);
 132}
 133
 134static void spi_cs_deactivate(struct udevice *dev)
 135{
 136        struct udevice *bus = dev_get_parent(dev);
 137        struct xilinx_spi_priv *priv = dev_get_priv(bus);
 138        struct xilinx_spi_regs *regs = priv->regs;
 139
 140        writel(SPISSR_OFF, &regs->spissr);
 141}
 142
 143static int xilinx_spi_claim_bus(struct udevice *dev)
 144{
 145        struct udevice *bus = dev_get_parent(dev);
 146        struct xilinx_spi_priv *priv = dev_get_priv(bus);
 147        struct xilinx_spi_regs *regs = priv->regs;
 148
 149        writel(SPISSR_OFF, &regs->spissr);
 150        writel(XILSPI_SPICR_DFLT_ON, &regs->spicr);
 151
 152        return 0;
 153}
 154
 155static int xilinx_spi_release_bus(struct udevice *dev)
 156{
 157        struct udevice *bus = dev_get_parent(dev);
 158        struct xilinx_spi_priv *priv = dev_get_priv(bus);
 159        struct xilinx_spi_regs *regs = priv->regs;
 160
 161        writel(SPISSR_OFF, &regs->spissr);
 162        writel(XILSPI_SPICR_DFLT_OFF, &regs->spicr);
 163
 164        return 0;
 165}
 166
 167static u32 xilinx_spi_fill_txfifo(struct udevice *bus, const u8 *txp,
 168                                  u32 txbytes)
 169{
 170        struct xilinx_spi_priv *priv = dev_get_priv(bus);
 171        struct xilinx_spi_regs *regs = priv->regs;
 172        unsigned char d;
 173        u32 i = 0;
 174
 175        while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) &&
 176               i < priv->fifo_depth) {
 177                d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
 178                debug("spi_xfer: tx:%x ", d);
 179                /* write out and wait for processing (receive data) */
 180                writel(d & SPIDTR_8BIT_MASK, &regs->spidtr);
 181                txbytes--;
 182                i++;
 183        }
 184
 185        return i;
 186}
 187
 188static u32 xilinx_spi_read_rxfifo(struct udevice *bus, u8 *rxp, u32 rxbytes)
 189{
 190        struct xilinx_spi_priv *priv = dev_get_priv(bus);
 191        struct xilinx_spi_regs *regs = priv->regs;
 192        unsigned char d;
 193        unsigned int i = 0;
 194
 195        while (rxbytes && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) {
 196                d = readl(&regs->spidrr) & SPIDRR_8BIT_MASK;
 197                if (rxp)
 198                        *rxp++ = d;
 199                debug("spi_xfer: rx:%x\n", d);
 200                rxbytes--;
 201                i++;
 202        }
 203        debug("Rx_done\n");
 204
 205        return i;
 206}
 207
 208static void xilinx_spi_startup_block(struct udevice *dev, unsigned int bytes,
 209                                     const void *dout, void *din)
 210{
 211        struct udevice *bus = dev_get_parent(dev);
 212        struct xilinx_spi_priv *priv = dev_get_priv(bus);
 213        struct xilinx_spi_regs *regs = priv->regs;
 214        struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 215        const unsigned char *txp = dout;
 216        unsigned char *rxp = din;
 217        u32 reg, count;
 218        u32 txbytes = bytes;
 219        u32 rxbytes = bytes;
 220
 221        /*
 222         * This loop runs two times. First time to send the command.
 223         * Second time to transfer data. After transferring data,
 224         * it sets txp to the initial value for the normal operation.
 225         */
 226        for ( ; priv->startup < 2; priv->startup++) {
 227                count = xilinx_spi_fill_txfifo(bus, txp, txbytes);
 228                reg = readl(&regs->spicr) & ~SPICR_MASTER_INHIBIT;
 229                writel(reg, &regs->spicr);
 230                count = xilinx_spi_read_rxfifo(bus, rxp, rxbytes);
 231                txp = din;
 232
 233                if (priv->startup) {
 234                        spi_cs_deactivate(dev);
 235                        spi_cs_activate(dev, slave_plat->cs);
 236                        txp = dout;
 237                }
 238        }
 239}
 240
 241static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen,
 242                            const void *dout, void *din, unsigned long flags)
 243{
 244        struct udevice *bus = dev_get_parent(dev);
 245        struct xilinx_spi_priv *priv = dev_get_priv(bus);
 246        struct xilinx_spi_regs *regs = priv->regs;
 247        struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 248        /* assume spi core configured to do 8 bit transfers */
 249        unsigned int bytes = bitlen / XILSPI_MAX_XFER_BITS;
 250        const unsigned char *txp = dout;
 251        unsigned char *rxp = din;
 252        u32 txbytes = bytes;
 253        u32 rxbytes = bytes;
 254        u32 reg, count, timeout;
 255        int ret;
 256
 257        debug("spi_xfer: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n",
 258              bus->seq, slave_plat->cs, bitlen, bytes, flags);
 259
 260        if (bitlen == 0)
 261                goto done;
 262
 263        if (bitlen % XILSPI_MAX_XFER_BITS) {
 264                printf("XILSPI warning: Not a multiple of %d bits\n",
 265                       XILSPI_MAX_XFER_BITS);
 266                flags |= SPI_XFER_END;
 267                goto done;
 268        }
 269
 270        if (flags & SPI_XFER_BEGIN)
 271                spi_cs_activate(dev, slave_plat->cs);
 272
 273        /*
 274         * This is the work around for the startup block issue in
 275         * the spi controller. SPI clock is passing through STARTUP
 276         * block to FLASH. STARTUP block don't provide clock as soon
 277         * as QSPI provides command. So first command fails.
 278         */
 279        xilinx_spi_startup_block(dev, bytes, dout, din);
 280
 281        while (txbytes && rxbytes) {
 282                count = xilinx_spi_fill_txfifo(bus, txp, txbytes);
 283                reg = readl(&regs->spicr) & ~SPICR_MASTER_INHIBIT;
 284                writel(reg, &regs->spicr);
 285                txbytes -= count;
 286                if (txp)
 287                        txp += count;
 288
 289                ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true,
 290                                        XILINX_SPISR_TIMEOUT, false);
 291                if (ret < 0) {
 292                        printf("XILSPI error: Xfer timeout\n");
 293                        return ret;
 294                }
 295
 296                debug("txbytes:0x%x,txp:0x%p\n", txbytes, txp);
 297                count = xilinx_spi_read_rxfifo(bus, rxp, rxbytes);
 298                rxbytes -= count;
 299                if (rxp)
 300                        rxp += count;
 301                debug("rxbytes:0x%x rxp:0x%p\n", rxbytes, rxp);
 302        }
 303
 304 done:
 305        if (flags & SPI_XFER_END)
 306                spi_cs_deactivate(dev);
 307
 308        return 0;
 309}
 310
 311static int xilinx_spi_set_speed(struct udevice *bus, uint speed)
 312{
 313        struct xilinx_spi_priv *priv = dev_get_priv(bus);
 314
 315        priv->freq = speed;
 316
 317        debug("xilinx_spi_set_speed: regs=%p, speed=%d\n", priv->regs,
 318              priv->freq);
 319
 320        return 0;
 321}
 322
 323static int xilinx_spi_set_mode(struct udevice *bus, uint mode)
 324{
 325        struct xilinx_spi_priv *priv = dev_get_priv(bus);
 326        struct xilinx_spi_regs *regs = priv->regs;
 327        uint32_t spicr;
 328
 329        spicr = readl(&regs->spicr);
 330        if (mode & SPI_LSB_FIRST)
 331                spicr |= SPICR_LSB_FIRST;
 332        if (mode & SPI_CPHA)
 333                spicr |= SPICR_CPHA;
 334        if (mode & SPI_CPOL)
 335                spicr |= SPICR_CPOL;
 336        if (mode & SPI_LOOP)
 337                spicr |= SPICR_LOOP;
 338
 339        writel(spicr, &regs->spicr);
 340        priv->mode = mode;
 341
 342        debug("xilinx_spi_set_mode: regs=%p, mode=%d\n", priv->regs,
 343              priv->mode);
 344
 345        return 0;
 346}
 347
 348static const struct dm_spi_ops xilinx_spi_ops = {
 349        .claim_bus      = xilinx_spi_claim_bus,
 350        .release_bus    = xilinx_spi_release_bus,
 351        .xfer           = xilinx_spi_xfer,
 352        .set_speed      = xilinx_spi_set_speed,
 353        .set_mode       = xilinx_spi_set_mode,
 354};
 355
 356static const struct udevice_id xilinx_spi_ids[] = {
 357        { .compatible = "xlnx,xps-spi-2.00.a" },
 358        { .compatible = "xlnx,xps-spi-2.00.b" },
 359        { }
 360};
 361
 362U_BOOT_DRIVER(xilinx_spi) = {
 363        .name   = "xilinx_spi",
 364        .id     = UCLASS_SPI,
 365        .of_match = xilinx_spi_ids,
 366        .ops    = &xilinx_spi_ops,
 367        .priv_auto_alloc_size = sizeof(struct xilinx_spi_priv),
 368        .probe  = xilinx_spi_probe,
 369};
 370