1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Configuation settings for the Freescale MCF52277 EVB board. 4 * 5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 */ 8 9/* 10 * board/config.h - configuration options, board specific 11 */ 12 13#ifndef _M52277EVB_H 14#define _M52277EVB_H 15 16/* 17 * High Level Configuration Options 18 * (easy to change) 19 */ 20 21#define CONFIG_MCFUART 22#define CONFIG_SYS_UART_PORT (0) 23 24#undef CONFIG_WATCHDOG 25 26#define CONFIG_TIMESTAMP /* Print image info with timestamp */ 27 28/* 29 * BOOTP options 30 */ 31#define CONFIG_BOOTP_BOOTFILESIZE 32 33#define CONFIG_HOSTNAME "M52277EVB" 34#define CONFIG_SYS_UBOOT_END 0x3FFFF 35#define CONFIG_SYS_LOAD_ADDR2 0x40010007 36#ifdef CONFIG_SYS_STMICRO_BOOT 37/* ST Micro serial flash */ 38#define CONFIG_EXTRA_ENV_SETTINGS \ 39 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 40 "loadaddr=0x40010000\0" \ 41 "uboot=u-boot.bin\0" \ 42 "load=loadb ${loadaddr} ${baudrate};" \ 43 "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ 44 "upd=run load; run prog\0" \ 45 "prog=sf probe 0:2 10000 1;" \ 46 "sf erase 0 30000;" \ 47 "sf write ${loadaddr} 0 30000;" \ 48 "save\0" \ 49 "" 50#endif 51#ifdef CONFIG_SYS_SPANSION_BOOT 52#define CONFIG_EXTRA_ENV_SETTINGS \ 53 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 54 "loadaddr=0x40010000\0" \ 55 "uboot=u-boot.bin\0" \ 56 "load=loadb ${loadaddr} ${baudrate}\0" \ 57 "upd=run load; run prog\0" \ 58 "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ 59 " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ 60 "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ 61 __stringify(CONFIG_SYS_UBOOT_END) ";" \ 62 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ 63 " ${filesize}; save\0" \ 64 "updsbf=run loadsbf; run progsbf\0" \ 65 "loadsbf=loadb ${loadaddr} ${baudrate};" \ 66 "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ 67 "progsbf=sf probe 0:2 10000 1;" \ 68 "sf erase 0 30000;" \ 69 "sf write ${loadaddr} 0 30000;" \ 70 "" 71#endif 72 73/* LCD */ 74#ifdef CONFIG_CMD_BMP 75#define CONFIG_SPLASH_SCREEN 76#define CONFIG_LCD_LOGO 77#define CONFIG_SHARP_LQ035Q7DH06 78#endif 79 80/* USB */ 81#ifdef CONFIG_CMD_USB 82#define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000 83#define CONFIG_SYS_USB_EHCI_CPU_INIT 84#endif 85 86/* Realtime clock */ 87#define CONFIG_MCFRTC 88#undef RTC_DEBUG 89#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 90 91/* Timer */ 92#define CONFIG_MCFTMR 93#undef CONFIG_MCFPIT 94 95/* I2c */ 96#define CONFIG_SYS_I2C 97#define CONFIG_SYS_I2C_FSL 98#define CONFIG_SYS_FSL_I2C_SPEED 80000 99#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 100#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 101#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 102 103/* DSPI and Serial Flash */ 104#define CONFIG_CF_DSPI 105#define CONFIG_SYS_SBFHDR_SIZE 0x7 106 107/* Input, PCI, Flexbus, and VCO */ 108#define CONFIG_EXTRA_CLOCK 109 110#define CONFIG_SYS_INPUT_CLKSRC 16000000 111 112#define CONFIG_PRAM 2048 /* 2048 KB */ 113 114#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 115 116#define CONFIG_SYS_MBAR 0xFC000000 117 118/* 119 * Low Level Configuration Settings 120 * (address mappings, register initial values, etc.) 121 * You should know what you are doing if you make changes here. 122 */ 123 124/* 125 * Definitions for initial stack pointer and data area (in DPRAM) 126 */ 127#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 128#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 129#define CONFIG_SYS_INIT_RAM_CTRL 0x221 130#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 131#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32) 132#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 133 134/* 135 * Start addresses for the final memory configuration 136 * (Set up by the startup code) 137 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 138 */ 139#define CONFIG_SYS_SDRAM_BASE 0x40000000 140#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ 141#define CONFIG_SYS_SDRAM_CFG1 0x43711630 142#define CONFIG_SYS_SDRAM_CFG2 0x56670000 143#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 144#define CONFIG_SYS_SDRAM_EMOD 0x81810000 145#define CONFIG_SYS_SDRAM_MODE 0x00CD0000 146#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00 147 148#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 149#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 150 151#ifdef CONFIG_CF_SBF 152# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 153#else 154# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 155#endif 156#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 157#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 158#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 159 160/* Initial Memory map for Linux */ 161#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 162#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 163 164/* 165 * Configuration for environment 166 * Environment is not embedded in u-boot. First time runing may have env 167 * crc error warning if there is no correct environment on the flash. 168 */ 169#define CONFIG_ENV_OVERWRITE 1 170 171/*----------------------------------------------------------------------- 172 * FLASH organization 173 */ 174#ifdef CONFIG_SYS_STMICRO_BOOT 175# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 176# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 177#endif 178#ifdef CONFIG_SYS_SPANSION_BOOT 179# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 180# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 181#endif 182 183#ifdef CONFIG_SYS_FLASH_CFI 184# define CONFIG_FLASH_SPANSION_S29WS_N 1 185# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 186# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 187# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 188# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 189# define CONFIG_SYS_FLASH_CHECKSUM 190# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 191#endif 192 193#define LDS_BOARD_TEXT \ 194 arch/m68k/cpu/mcf5227x/built-in.o (.text*) \ 195 arch/m68k/lib/built-in.o (.text*) 196 197/* 198 * This is setting for JFFS2 support in u-boot. 199 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 200 */ 201#ifdef CONFIG_CMD_JFFS2 202# define CONFIG_JFFS2_DEV "nor0" 203# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000) 204# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000) 205#endif 206 207/*----------------------------------------------------------------------- 208 * Cache Configuration 209 */ 210#define CONFIG_SYS_CACHELINE_SIZE 16 211 212#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 213 CONFIG_SYS_INIT_RAM_SIZE - 8) 214#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 215 CONFIG_SYS_INIT_RAM_SIZE - 4) 216#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 217#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 218 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 219 CF_ACR_EN | CF_ACR_SM_ALL) 220#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 221 CF_CACR_DISD | CF_CACR_INVI | \ 222 CF_CACR_CEIB | CF_CACR_DCM | \ 223 CF_CACR_EUSP) 224 225/*----------------------------------------------------------------------- 226 * Memory bank definitions 227 */ 228/* 229 * CS0 - NOR Flash 230 * CS1 - Available 231 * CS2 - Available 232 * CS3 - Available 233 * CS4 - Available 234 * CS5 - Available 235 */ 236 237#ifdef CONFIG_CF_SBF 238#define CONFIG_SYS_CS0_BASE 0x04000000 239#define CONFIG_SYS_CS0_MASK 0x00FF0001 240#define CONFIG_SYS_CS0_CTRL 0x00001FA0 241#else 242#define CONFIG_SYS_CS0_BASE 0x00000000 243#define CONFIG_SYS_CS0_MASK 0x00FF0001 244#define CONFIG_SYS_CS0_CTRL 0x00001FA0 245#endif 246 247#endif /* _M52277EVB_H */ 248