1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 3 * Hayden Fraser (Hayden.Fraser@freescale.com) 4 */ 5 6#ifndef _M5253DEMO_H 7#define _M5253DEMO_H 8 9#define CONFIG_MCFTMR 10 11#define CONFIG_MCFUART 12#define CONFIG_SYS_UART_PORT (0) 13 14#undef CONFIG_WATCHDOG /* disable watchdog */ 15 16 17/* Configuration for environment 18 * Environment is embedded in u-boot in the second sector of the flash 19 */ 20 21#define LDS_BOARD_TEXT \ 22 . = DEFINED(env_offset) ? env_offset : .; \ 23 env/embedded.o(.text*); 24 25/* 26 * Command line configuration. 27 */ 28 29#ifdef CONFIG_IDE 30/* ATA */ 31# define CONFIG_IDE_RESET 1 32# define CONFIG_IDE_PREINIT 1 33# define CONFIG_ATAPI 34# undef CONFIG_LBA48 35 36# define CONFIG_SYS_IDE_MAXBUS 1 37# define CONFIG_SYS_IDE_MAXDEVICE 2 38 39# define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800) 40# define CONFIG_SYS_ATA_IDE0_OFFSET 0 41 42# define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 43# define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 44# define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 45# define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 46#endif 47 48#define CONFIG_DRIVER_DM9000 49#ifdef CONFIG_DRIVER_DM9000 50# define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300) 51# define DM9000_IO CONFIG_DM9000_BASE 52# define DM9000_DATA (CONFIG_DM9000_BASE + 4) 53# undef CONFIG_DM9000_DEBUG 54# define CONFIG_DM9000_BYTE_SWAPPED 55 56# define CONFIG_OVERWRITE_ETHADDR_ONCE 57 58# define CONFIG_EXTRA_ENV_SETTINGS \ 59 "netdev=eth0\0" \ 60 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 61 "loadaddr=10000\0" \ 62 "u-boot=u-boot.bin\0" \ 63 "load=tftp ${loadaddr) ${u-boot}\0" \ 64 "upd=run load; run prog\0" \ 65 "prog=prot off 0xff800000 0xff82ffff;" \ 66 "era 0xff800000 0xff82ffff;" \ 67 "cp.b ${loadaddr} 0xff800000 ${filesize};" \ 68 "save\0" \ 69 "" 70#endif 71 72#define CONFIG_HOSTNAME "M5253DEMO" 73 74/* I2C */ 75#define CONFIG_SYS_I2C 76#define CONFIG_SYS_I2C_FSL 77#define CONFIG_SYS_FSL_I2C_SPEED 80000 78#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 79#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280 80#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 81#define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C)) 82#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) 83#define CONFIG_SYS_I2C_PINMUX_SET (0) 84 85#define CONFIG_SYS_LOAD_ADDR 0x00100000 86 87#define CONFIG_SYS_MEMTEST_START 0x400 88#define CONFIG_SYS_MEMTEST_END 0x380000 89 90#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ 91#define CONFIG_SYS_FAST_CLK 92#ifdef CONFIG_SYS_FAST_CLK 93# define CONFIG_SYS_PLLCR 0x1243E054 94# define CONFIG_SYS_CLK 140000000 95#else 96# define CONFIG_SYS_PLLCR 0x135a4140 97# define CONFIG_SYS_CLK 70000000 98#endif 99 100/* 101 * Low Level Configuration Settings 102 * (address mappings, register initial values, etc.) 103 * You should know what you are doing if you make changes here. 104 */ 105 106#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 107#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ 108 109/* 110 * Definitions for initial stack pointer and data area (in DPRAM) 111 */ 112#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 113#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 114#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 115#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 116 117/* 118 * Start addresses for the final memory configuration 119 * (Set up by the startup code) 120 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 121 */ 122#define CONFIG_SYS_SDRAM_BASE 0x00000000 123#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 124 125#ifdef CONFIG_MONITOR_IS_IN_RAM 126# define CONFIG_SYS_MONITOR_BASE 0x20000 127#else 128# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 129#endif 130 131#define CONFIG_SYS_MONITOR_LEN 0x40000 132#define CONFIG_SYS_MALLOC_LEN (256 << 10) 133#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) 134 135/* 136 * For booting Linux, the board info and command line data 137 * have to be in the first 8 MB of memory, since this is 138 * the maximum mapped by the Linux kernel during initialization ?? 139 */ 140#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 141#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 142 143/* FLASH organization */ 144#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 145#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 146#define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */ 147#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 148 149#define FLASH_SST6401B 0x200 150#define SST_ID_xF6401B 0x236D236D 151 152#ifdef CONFIG_SYS_FLASH_CFI 153/* 154 * Unable to use CFI driver, due to incompatible sector erase command by SST. 155 * Amd/Atmel use 0x30 for sector erase, SST use 0x50. 156 * 0x30 is block erase in SST 157 */ 158# define CONFIG_SYS_FLASH_SIZE 0x800000 159# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 160# define CONFIG_FLASH_CFI_LEGACY 161#else 162# define CONFIG_SYS_SST_SECT 2048 163# define CONFIG_SYS_SST_SECTSZ 0x1000 164# define CONFIG_SYS_FLASH_WRITE_TOUT 500 165#endif 166 167/* Cache Configuration */ 168#define CONFIG_SYS_CACHELINE_SIZE 16 169 170#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 171 CONFIG_SYS_INIT_RAM_SIZE - 8) 172#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 173 CONFIG_SYS_INIT_RAM_SIZE - 4) 174#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) 175#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ 176 CF_ADDRMASK(8) | \ 177 CF_ACR_EN | CF_ACR_SM_ALL) 178#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ 179 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 180 CF_ACR_EN | CF_ACR_SM_ALL) 181#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ 182 CF_CACR_DBWE) 183 184/* Port configuration */ 185#define CONFIG_SYS_FECI2C 0xF0 186 187#define CONFIG_SYS_CS0_BASE 0xFF800000 188#define CONFIG_SYS_CS0_MASK 0x007F0021 189#define CONFIG_SYS_CS0_CTRL 0x00001D80 190 191#define CONFIG_SYS_CS1_BASE 0xE0000000 192#define CONFIG_SYS_CS1_MASK 0x00000001 193#define CONFIG_SYS_CS1_CTRL 0x00003DD8 194 195/*----------------------------------------------------------------------- 196 * Port configuration 197 */ 198#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ 199#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ 200#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ 201#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ 202#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ 203#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ 204#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ 205 206#endif /* _M5253DEMO_H */ 207