1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Configuation settings for the Freescale MCF54455 EVB board. 4 * 5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 */ 8 9/* 10 * board/config.h - configuration options, board specific 11 */ 12 13#ifndef _M54455EVB_H 14#define _M54455EVB_H 15 16/* 17 * High Level Configuration Options 18 * (easy to change) 19 */ 20#define CONFIG_M54455EVB /* M54455EVB board */ 21 22#define CONFIG_MCFUART 23#define CONFIG_SYS_UART_PORT (0) 24 25#define LDS_BOARD_TEXT board/freescale/m54455evb/sbf_dram_init.o (.text*) 26 27#undef CONFIG_WATCHDOG 28 29#define CONFIG_TIMESTAMP /* Print image info with timestamp */ 30 31/* 32 * BOOTP options 33 */ 34#define CONFIG_BOOTP_BOOTFILESIZE 35 36/* Network configuration */ 37#define CONFIG_MCFFEC 38#ifdef CONFIG_MCFFEC 39# define CONFIG_MII_INIT 1 40# define CONFIG_SYS_DISCOVER_PHY 41# define CONFIG_SYS_RX_ETH_BUFFER 8 42# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 43 44# define CONFIG_SYS_FEC0_PINMUX 0 45# define CONFIG_SYS_FEC1_PINMUX 0 46# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 47# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE 48# define MCFFEC_TOUT_LOOP 50000 49# define CONFIG_HAS_ETH1 50 51# define CONFIG_ETHPRIME "FEC0" 52# define CONFIG_IPADDR 192.162.1.2 53# define CONFIG_NETMASK 255.255.255.0 54# define CONFIG_SERVERIP 192.162.1.1 55# define CONFIG_GATEWAYIP 192.162.1.1 56 57/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 58# ifndef CONFIG_SYS_DISCOVER_PHY 59# define FECDUPLEX FULL 60# define FECSPEED _100BASET 61# else 62# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 63# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 64# endif 65# endif /* CONFIG_SYS_DISCOVER_PHY */ 66#endif 67 68#define CONFIG_HOSTNAME "M54455EVB" 69#ifdef CONFIG_SYS_STMICRO_BOOT 70/* ST Micro serial flash */ 71#define CONFIG_SYS_LOAD_ADDR2 0x40010013 72#define CONFIG_EXTRA_ENV_SETTINGS \ 73 "netdev=eth0\0" \ 74 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 75 "loadaddr=0x40010000\0" \ 76 "sbfhdr=sbfhdr.bin\0" \ 77 "uboot=u-boot.bin\0" \ 78 "load=tftp ${loadaddr} ${sbfhdr};" \ 79 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 80 "upd=run load; run prog\0" \ 81 "prog=sf probe 0:1 1000000 3;" \ 82 "sf erase 0 30000;" \ 83 "sf write ${loadaddr} 0 0x30000;" \ 84 "save\0" \ 85 "" 86#else 87/* Atmel and Intel */ 88#ifdef CONFIG_SYS_ATMEL_BOOT 89# define CONFIG_SYS_UBOOT_END 0x0403FFFF 90#elif defined(CONFIG_SYS_INTEL_BOOT) 91# define CONFIG_SYS_UBOOT_END 0x3FFFF 92#endif 93#define CONFIG_EXTRA_ENV_SETTINGS \ 94 "netdev=eth0\0" \ 95 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 96 "loadaddr=0x40010000\0" \ 97 "uboot=u-boot.bin\0" \ 98 "load=tftp ${loadaddr} ${uboot}\0" \ 99 "upd=run load; run prog\0" \ 100 "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ 101 " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ 102 "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ 103 __stringify(CONFIG_SYS_UBOOT_END) ";" \ 104 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ 105 " ${filesize}; save\0" \ 106 "" 107#endif 108 109/* ATA configuration */ 110#define CONFIG_IDE_RESET 1 111#define CONFIG_IDE_PREINIT 1 112#define CONFIG_ATAPI 113#undef CONFIG_LBA48 114 115#define CONFIG_SYS_IDE_MAXBUS 1 116#define CONFIG_SYS_IDE_MAXDEVICE 2 117 118#define CONFIG_SYS_ATA_BASE_ADDR 0x90000000 119#define CONFIG_SYS_ATA_IDE0_OFFSET 0 120 121#define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 122#define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 123#define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 124#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 125 126/* Realtime clock */ 127#define CONFIG_MCFRTC 128#undef RTC_DEBUG 129#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 130 131/* Timer */ 132#define CONFIG_MCFTMR 133#undef CONFIG_MCFPIT 134 135/* I2c */ 136#define CONFIG_SYS_I2C 137#define CONFIG_SYS_I2C_FSL 138#define CONFIG_SYS_FSL_I2C_SPEED 80000 139#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 140#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 141#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 142 143/* DSPI and Serial Flash */ 144#define CONFIG_CF_DSPI 145#define CONFIG_SYS_SBFHDR_SIZE 0x13 146 147/* PCI */ 148#ifdef CONFIG_CMD_PCI 149#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 150 151#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4 152 153#define CONFIG_SYS_PCI_MEM_BUS 0xA0000000 154#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS 155#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 156 157#define CONFIG_SYS_PCI_IO_BUS 0xB1000000 158#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS 159#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 160 161#define CONFIG_SYS_PCI_CFG_BUS 0xB0000000 162#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS 163#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 164#endif 165 166/* FPGA - Spartan 2 */ 167/* experiment 168#define CONFIG_FPGA_COUNT 1 169#define CONFIG_SYS_FPGA_PROG_FEEDBACK 170#define CONFIG_SYS_FPGA_CHECK_CTRLC 171*/ 172 173/* Input, PCI, Flexbus, and VCO */ 174#define CONFIG_EXTRA_CLOCK 175 176#define CONFIG_PRAM 2048 /* 2048 KB */ 177 178#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 179 180#define CONFIG_SYS_MBAR 0xFC000000 181 182/* 183 * Low Level Configuration Settings 184 * (address mappings, register initial values, etc.) 185 * You should know what you are doing if you make changes here. 186 */ 187 188/*----------------------------------------------------------------------- 189 * Definitions for initial stack pointer and data area (in DPRAM) 190 */ 191#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 192#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 193#define CONFIG_SYS_INIT_RAM_CTRL 0x221 194#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 195#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 196#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 197 198/*----------------------------------------------------------------------- 199 * Start addresses for the final memory configuration 200 * (Set up by the startup code) 201 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 202 */ 203#define CONFIG_SYS_SDRAM_BASE 0x40000000 204#define CONFIG_SYS_SDRAM_BASE1 0x48000000 205#define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */ 206#define CONFIG_SYS_SDRAM_CFG1 0x65311610 207#define CONFIG_SYS_SDRAM_CFG2 0x59670000 208#define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000 209#define CONFIG_SYS_SDRAM_EMOD 0x40010000 210#define CONFIG_SYS_SDRAM_MODE 0x00010033 211#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA 212 213#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 214#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 215 216#ifdef CONFIG_CF_SBF 217# define CONFIG_SERIAL_BOOT 218# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 219#else 220# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 221#endif 222#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 223#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 224 225/* Reserve 256 kB for malloc() */ 226#define CONFIG_SYS_MALLOC_LEN (256 << 10) 227 228/* 229 * For booting Linux, the board info and command line data 230 * have to be in the first 8 MB of memory, since this is 231 * the maximum mapped by the Linux kernel during initialization ?? 232 */ 233/* Initial Memory map for Linux */ 234#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 235 236/* 237 * Configuration for environment 238 * Environment is not embedded in u-boot. First time runing may have env 239 * crc error warning if there is no correct environment on the flash. 240 */ 241#undef CONFIG_ENV_OVERWRITE 242 243/*----------------------------------------------------------------------- 244 * FLASH organization 245 */ 246#ifdef CONFIG_SYS_STMICRO_BOOT 247# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 248# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE 249#endif 250#ifdef CONFIG_SYS_ATMEL_BOOT 251# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 252# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 253# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE 254#endif 255#ifdef CONFIG_SYS_INTEL_BOOT 256# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 257# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 258# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE 259#endif 260 261#ifdef CONFIG_SYS_FLASH_CFI 262 263# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 264# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT 265# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 266# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 267# define CONFIG_SYS_FLASH_CHECKSUM 268# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } 269# define CONFIG_FLASH_CFI_LEGACY 270 271#ifdef CONFIG_FLASH_CFI_LEGACY 272# define CONFIG_SYS_ATMEL_REGION 4 273# define CONFIG_SYS_ATMEL_TOTALSECT 11 274# define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7} 275# define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} 276#endif 277#endif 278 279/* 280 * This is setting for JFFS2 support in u-boot. 281 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 282 */ 283#ifdef CONFIG_CMD_JFFS2 284#ifdef CF_STMICRO_BOOT 285# define CONFIG_JFFS2_DEV "nor1" 286# define CONFIG_JFFS2_PART_SIZE 0x01000000 287# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000) 288#endif 289#ifdef CONFIG_SYS_ATMEL_BOOT 290# define CONFIG_JFFS2_DEV "nor1" 291# define CONFIG_JFFS2_PART_SIZE 0x01000000 292# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000) 293#endif 294#ifdef CONFIG_SYS_INTEL_BOOT 295# define CONFIG_JFFS2_DEV "nor0" 296# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) 297# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) 298#endif 299#endif 300 301/*----------------------------------------------------------------------- 302 * Cache Configuration 303 */ 304#define CONFIG_SYS_CACHELINE_SIZE 16 305 306#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 307 CONFIG_SYS_INIT_RAM_SIZE - 8) 308#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 309 CONFIG_SYS_INIT_RAM_SIZE - 4) 310#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 311#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 312#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 313 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 314 CF_ACR_EN | CF_ACR_SM_ALL) 315#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 316 CF_CACR_ICINVA | CF_CACR_EUSP) 317#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 318 CF_CACR_DEC | CF_CACR_DDCM_P | \ 319 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 320 321/*----------------------------------------------------------------------- 322 * Memory bank definitions 323 */ 324/* 325 * CS0 - NOR Flash 1, 2, 4, or 8MB 326 * CS1 - CompactFlash and registers 327 * CS2 - CPLD 328 * CS3 - FPGA 329 * CS4 - Available 330 * CS5 - Available 331 */ 332 333#if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT) 334 /* Atmel Flash */ 335#define CONFIG_SYS_CS0_BASE 0x04000000 336#define CONFIG_SYS_CS0_MASK 0x00070001 337#define CONFIG_SYS_CS0_CTRL 0x00001140 338/* Intel Flash */ 339#define CONFIG_SYS_CS1_BASE 0x00000000 340#define CONFIG_SYS_CS1_MASK 0x01FF0001 341#define CONFIG_SYS_CS1_CTRL 0x00000D60 342 343#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE 344#else 345/* Intel Flash */ 346#define CONFIG_SYS_CS0_BASE 0x00000000 347#define CONFIG_SYS_CS0_MASK 0x01FF0001 348#define CONFIG_SYS_CS0_CTRL 0x00000D60 349 /* Atmel Flash */ 350#define CONFIG_SYS_CS1_BASE 0x04000000 351#define CONFIG_SYS_CS1_MASK 0x00070001 352#define CONFIG_SYS_CS1_CTRL 0x00001140 353 354#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE 355#endif 356 357/* CPLD */ 358#define CONFIG_SYS_CS2_BASE 0x08000000 359#define CONFIG_SYS_CS2_MASK 0x00070001 360#define CONFIG_SYS_CS2_CTRL 0x003f1140 361 362/* FPGA */ 363#define CONFIG_SYS_CS3_BASE 0x09000000 364#define CONFIG_SYS_CS3_MASK 0x00070001 365#define CONFIG_SYS_CS3_CTRL 0x00000020 366 367#endif /* _M54455EVB_H */ 368