LXR uboot/include/configs/MPC832XEMDS.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4 */
   5
   6#ifndef __CONFIG_H
   7#define __CONFIG_H
   8
   9/*
  10 * High Level Configuration Options
  11 */
  12#define CONFIG_E300             1       /* E300 family */
  13
  14/*
  15 * System IO Config
  16 */
  17#define CONFIG_SYS_SICRL                0x00000000
  18
  19/*
  20 * DDR Setup
  21 */
  22#define CONFIG_SYS_SDRAM_BASE   0x00000000      /* DDR is system memory */
  23#define CONFIG_SYS_DDRCDR       0x73000002      /* DDR II voltage is 1.8V */
  24
  25#undef CONFIG_SPD_EEPROM
  26#if defined(CONFIG_SPD_EEPROM)
  27/* Determine DDR configuration from I2C interface
  28 */
  29#define SPD_EEPROM_ADDRESS      0x51    /* DDR SODIMM */
  30#else
  31/* Manually set up DDR parameters
  32 */
  33#define CONFIG_SYS_DDR_SIZE             128     /* MB */
  34#define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  35                                        | CSCONFIG_AP \
  36                                        | CSCONFIG_ODT_WR_CFG \
  37                                        | CSCONFIG_ROW_BIT_13 \
  38                                        | CSCONFIG_COL_BIT_10)
  39                                        /* 0x80840102 */
  40#define CONFIG_SYS_DDR_TIMING_0         ((0 << TIMING_CFG0_RWT_SHIFT) \
  41                                        | (0 << TIMING_CFG0_WRT_SHIFT) \
  42                                        | (0 << TIMING_CFG0_RRT_SHIFT) \
  43                                        | (0 << TIMING_CFG0_WWT_SHIFT) \
  44                                        | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  45                                        | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  46                                        | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  47                                        | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  48                                        /* 0x00220802 */
  49#define CONFIG_SYS_DDR_TIMING_1         ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
  50                                        | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  51                                        | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
  52                                        | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  53                                        | (13 << TIMING_CFG1_REFREC_SHIFT) \
  54                                        | (3 << TIMING_CFG1_WRREC_SHIFT) \
  55                                        | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  56                                        | (2 << TIMING_CFG1_WRTORD_SHIFT))
  57                                        /* 0x3935D322 */
  58#define CONFIG_SYS_DDR_TIMING_2         ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
  59                                | (31 << TIMING_CFG2_CPO_SHIFT) \
  60                                | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  61                                | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  62                                | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  63                                | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  64                                | (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
  65                                /* 0x0F9048CA */
  66#define CONFIG_SYS_DDR_TIMING_3         0x00000000
  67#define CONFIG_SYS_DDR_CLK_CNTL         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  68                                        /* 0x02000000 */
  69#define CONFIG_SYS_DDR_MODE             ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
  70                                        | (0x0232 << SDRAM_MODE_SD_SHIFT))
  71                                        /* 0x44400232 */
  72#define CONFIG_SYS_DDR_MODE2            0x8000c000
  73#define CONFIG_SYS_DDR_INTERVAL         ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
  74                                        | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  75                                        /* 0x03200064 */
  76#define CONFIG_SYS_DDR_CS0_BNDS         0x00000007
  77#define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
  78                                        | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  79                                        | SDRAM_CFG_32_BE)
  80                                        /* 0x43080000 */
  81#define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
  82#endif
  83
  84/*
  85 * Memory test
  86 */
  87#undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  88#define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  89#define CONFIG_SYS_MEMTEST_END          0x00100000
  90
  91/*
  92 * The reserved memory
  93 */
  94#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  95
  96#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  97#define CONFIG_SYS_RAMBOOT
  98#else
  99#undef  CONFIG_SYS_RAMBOOT
 100#endif
 101
 102/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 103#define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 104#define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 105
 106/*
 107 * Initial RAM Base Address Setup
 108 */
 109#define CONFIG_SYS_INIT_RAM_LOCK        1
 110#define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000      /* Initial RAM addr */
 111#define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM */
 112#define CONFIG_SYS_GBL_DATA_OFFSET      \
 113                        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 114
 115/*
 116 * FLASH on the Local Bus
 117 */
 118#define CONFIG_SYS_FLASH_BASE   0xFE000000      /* FLASH base address */
 119#define CONFIG_SYS_FLASH_SIZE   16      /* FLASH size is 16M */
 120
 121
 122#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 123#define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
 124
 125#undef CONFIG_SYS_FLASH_CHECKSUM
 126
 127/*
 128 * BCSR on the Local Bus
 129 */
 130#define CONFIG_SYS_BCSR                 0xF8000000
 131                                        /* Access window base at BCSR base */
 132
 133
 134/*
 135 * Windows to access PIB via local bus
 136 */
 137                                        /* PIB window base 0xF8008000 */
 138#define CONFIG_SYS_PIB_BASE             0xF8008000
 139#define CONFIG_SYS_PIB_WINDOW_SIZE      (32 * 1024)
 140
 141/*
 142 * CS2 on Local Bus, to PIB
 143 */
 144
 145
 146/*
 147 * CS3 on Local Bus, to PIB
 148 */
 149
 150
 151/*
 152 * Serial Port
 153 */
 154#define CONFIG_SYS_NS16550_SERIAL
 155#define CONFIG_SYS_NS16550_REG_SIZE     1
 156#define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 157
 158#define CONFIG_SYS_BAUDRATE_TABLE  \
 159                {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 160
 161#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 162#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 163
 164/* I2C */
 165#define CONFIG_SYS_I2C
 166#define CONFIG_SYS_I2C_FSL
 167#define CONFIG_SYS_FSL_I2C_SPEED        400000
 168#define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 169#define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 170#define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 171
 172/*
 173 * Config on-board RTC
 174 */
 175#define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
 176#define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68 */
 177
 178/*
 179 * General PCI
 180 * Addresses are mapped 1-1.
 181 */
 182#define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 183#define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 184#define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 185#define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 186#define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 187#define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 188#define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 189#define CONFIG_SYS_PCI1_IO_PHYS         0xE0300000
 190#define CONFIG_SYS_PCI1_IO_SIZE         0x100000        /* 1M */
 191
 192#define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 193#define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 194#define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 195
 196#ifdef CONFIG_PCI
 197#define CONFIG_PCI_INDIRECT_BRIDGE
 198
 199#define CONFIG_83XX_PCI_STREAMING
 200
 201#undef CONFIG_EEPRO100
 202#undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 203#define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 204
 205#endif  /* CONFIG_PCI */
 206
 207/*
 208 * QE UEC ethernet configuration
 209 */
 210#define CONFIG_UEC_ETH
 211#define CONFIG_ETHPRIME         "UEC0"
 212
 213#define CONFIG_UEC_ETH1         /* ETH3 */
 214
 215#ifdef CONFIG_UEC_ETH1
 216#define CONFIG_SYS_UEC1_UCC_NUM 2       /* UCC3 */
 217#define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
 218#define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
 219#define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 220#define CONFIG_SYS_UEC1_PHY_ADDR        3
 221#define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 222#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 223#endif
 224
 225#define CONFIG_UEC_ETH2         /* ETH4 */
 226
 227#ifdef CONFIG_UEC_ETH2
 228#define CONFIG_SYS_UEC2_UCC_NUM 3       /* UCC4 */
 229#define CONFIG_SYS_UEC2_RX_CLK          QE_CLK7
 230#define CONFIG_SYS_UEC2_TX_CLK          QE_CLK8
 231#define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 232#define CONFIG_SYS_UEC2_PHY_ADDR        4
 233#define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 234#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 235#endif
 236
 237/*
 238 * Environment
 239 */
 240
 241#define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 242#define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 243
 244/*
 245 * BOOTP options
 246 */
 247#define CONFIG_BOOTP_BOOTFILESIZE
 248
 249/*
 250 * Command line configuration.
 251 */
 252
 253#undef CONFIG_WATCHDOG          /* watchdog disabled */
 254
 255/*
 256 * Miscellaneous configurable options
 257 */
 258#define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 259
 260/*
 261 * For booting Linux, the board info and command line data
 262 * have to be in the first 256 MB of memory, since this is
 263 * the maximum mapped by the Linux kernel during initialization.
 264 */
 265                                        /* Initial Memory map for Linux */
 266#define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 267#define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 268
 269#if defined(CONFIG_CMD_KGDB)
 270#define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 271#endif
 272
 273/*
 274 * Environment Configuration
 275 */ #define CONFIG_ENV_OVERWRITE
 276
 277#if defined(CONFIG_UEC_ETH)
 278#define CONFIG_HAS_ETH0
 279#define CONFIG_HAS_ETH1
 280#endif
 281
 282#define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 283
 284#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 285        "netdev=eth0\0"                                                 \
 286        "consoledev=ttyS0\0"                                            \
 287        "ramdiskaddr=1000000\0"                                         \
 288        "ramdiskfile=ramfs.83xx\0"                                      \
 289        "fdtaddr=780000\0"                                              \
 290        "fdtfile=mpc832x_mds.dtb\0"                                     \
 291        ""
 292
 293#define CONFIG_NFSBOOTCOMMAND                                           \
 294        "setenv bootargs root=/dev/nfs rw "                             \
 295                "nfsroot=$serverip:$rootpath "                          \
 296                "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 297                                                        "$netdev:off "  \
 298                "console=$consoledev,$baudrate $othbootargs;"           \
 299        "tftp $loadaddr $bootfile;"                                     \
 300        "tftp $fdtaddr $fdtfile;"                                       \
 301        "bootm $loadaddr - $fdtaddr"
 302
 303#define CONFIG_RAMBOOTCOMMAND                                           \
 304        "setenv bootargs root=/dev/ram rw "                             \
 305                "console=$consoledev,$baudrate $othbootargs;"           \
 306        "tftp $ramdiskaddr $ramdiskfile;"                               \
 307        "tftp $loadaddr $bootfile;"                                     \
 308        "tftp $fdtaddr $fdtfile;"                                       \
 309        "bootm $loadaddr $ramdiskaddr $fdtaddr"
 310
 311#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 312
 313#endif  /* __CONFIG_H */
 314