LXR uboot/include/configs/MPC8349EMDS.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * (C) Copyright 2006-2010
   4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5 */
   6
   7/*
   8 * mpc8349emds board configuration file
   9 *
  10 */
  11
  12#ifndef __CONFIG_H
  13#define __CONFIG_H
  14
  15/*
  16 * High Level Configuration Options
  17 */
  18#define CONFIG_E300             1       /* E300 Family */
  19
  20#undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  21#define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  22#define CONFIG_SYS_MEMTEST_END          0x00100000
  23
  24/*
  25 * DDR Setup
  26 */
  27#define CONFIG_DDR_ECC                  /* support DDR ECC function */
  28#define CONFIG_DDR_ECC_CMD              /* use DDR ECC user commands */
  29#define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
  30
  31/*
  32 * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
  33 * unselect it to use old spd_sdram.c
  34 */
  35#define CONFIG_SYS_SPD_BUS_NUM  0
  36#define SPD_EEPROM_ADDRESS1     0x52
  37#define SPD_EEPROM_ADDRESS2     0x51
  38#define CONFIG_DIMM_SLOTS_PER_CTLR      2
  39#define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  40#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  41#define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  42
  43/*
  44 * 32-bit data path mode.
  45 *
  46 * Please note that using this mode for devices with the real density of 64-bit
  47 * effectively reduces the amount of available memory due to the effect of
  48 * wrapping around while translating address to row/columns, for example in the
  49 * 256MB module the upper 128MB get aliased with contents of the lower
  50 * 128MB); normally this define should be used for devices with real 32-bit
  51 * data path.
  52 */
  53#undef CONFIG_DDR_32BIT
  54
  55#define CONFIG_SYS_SDRAM_BASE   0x00000000      /* DDR is system memory*/
  56#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
  57                                        | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  58#undef  CONFIG_DDR_2T_TIMING
  59
  60/*
  61 * DDRCDR - DDR Control Driver Register
  62 */
  63#define CONFIG_SYS_DDRCDR_VALUE 0x80080001
  64
  65#if defined(CONFIG_SPD_EEPROM)
  66/*
  67 * Determine DDR configuration from I2C interface.
  68 */
  69#define SPD_EEPROM_ADDRESS      0x51            /* DDR DIMM */
  70#else
  71/*
  72 * Manually set up DDR parameters
  73 */
  74#define CONFIG_SYS_DDR_SIZE             256             /* MB */
  75#if defined(CONFIG_DDR_II)
  76#define CONFIG_SYS_DDRCDR               0x80080001
  77#define CONFIG_SYS_DDR_CS2_BNDS         0x0000000f
  78#define CONFIG_SYS_DDR_CS2_CONFIG       0x80330102
  79#define CONFIG_SYS_DDR_TIMING_0         0x00220802
  80#define CONFIG_SYS_DDR_TIMING_1         0x38357322
  81#define CONFIG_SYS_DDR_TIMING_2         0x2f9048c8
  82#define CONFIG_SYS_DDR_TIMING_3         0x00000000
  83#define CONFIG_SYS_DDR_CLK_CNTL         0x02000000
  84#define CONFIG_SYS_DDR_MODE             0x47d00432
  85#define CONFIG_SYS_DDR_MODE2            0x8000c000
  86#define CONFIG_SYS_DDR_INTERVAL         0x03cf0080
  87#define CONFIG_SYS_DDR_SDRAM_CFG        0x43000000
  88#define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
  89#else
  90#define CONFIG_SYS_DDR_CS2_CONFIG       (CSCONFIG_EN \
  91                                | CSCONFIG_ROW_BIT_13 \
  92                                | CSCONFIG_COL_BIT_10)
  93#define CONFIG_SYS_DDR_TIMING_1 0x36332321
  94#define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
  95#define CONFIG_SYS_DDR_CONTROL  0xc2000000      /* unbuffered,no DYN_PWR */
  96#define CONFIG_SYS_DDR_INTERVAL 0x04060100      /* autocharge,no open page */
  97
  98#if defined(CONFIG_DDR_32BIT)
  99/* set burst length to 8 for 32-bit data path */
 100                                /* DLL,normal,seq,4/2.5, 8 burst len */
 101#define CONFIG_SYS_DDR_MODE     0x00000023
 102#else
 103/* the default burst length is 4 - for 64-bit data path */
 104                                /* DLL,normal,seq,4/2.5, 4 burst len */
 105#define CONFIG_SYS_DDR_MODE     0x00000022
 106#endif
 107#endif
 108#endif
 109
 110/*
 111 * SDRAM on the Local Bus
 112 */
 113#define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* Localbus SDRAM */
 114#define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 115
 116/*
 117 * FLASH on the Local Bus
 118 */
 119#define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 120#define CONFIG_SYS_FLASH_SIZE           32      /* max flash size in MB */
 121
 122
 123#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 124#define CONFIG_SYS_MAX_FLASH_SECT       256     /* max sectors per device */
 125
 126#undef CONFIG_SYS_FLASH_CHECKSUM
 127#define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 128#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 129
 130#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 131
 132#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 133#define CONFIG_SYS_RAMBOOT
 134#else
 135#undef  CONFIG_SYS_RAMBOOT
 136#endif
 137
 138/*
 139 * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
 140 */
 141#define CONFIG_SYS_BCSR                 0xE2400000
 142                                        /* Access window base at BCSR base */
 143
 144
 145#define CONFIG_SYS_INIT_RAM_LOCK        1
 146#define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 147#define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 148
 149#define CONFIG_SYS_GBL_DATA_OFFSET      \
 150                        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 151#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 152
 153#define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 154#define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 155
 156/*
 157 * Serial Port
 158 */
 159#define CONFIG_SYS_NS16550_SERIAL
 160#define CONFIG_SYS_NS16550_REG_SIZE    1
 161#define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 162
 163#define CONFIG_SYS_BAUDRATE_TABLE  \
 164                {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 165
 166#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
 167#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
 168
 169/* I2C */
 170#define CONFIG_SYS_I2C
 171#define CONFIG_SYS_I2C_FSL
 172#define CONFIG_SYS_FSL_I2C_SPEED        400000
 173#define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 174#define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 175#define CONFIG_SYS_FSL_I2C2_SPEED       400000
 176#define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 177#define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 178#define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 179
 180/* SPI */
 181#undef CONFIG_SOFT_SPI                  /* SPI bit-banged */
 182
 183/* GPIOs.  Used as SPI chip selects */
 184#define CONFIG_SYS_GPIO1_PRELIM
 185#define CONFIG_SYS_GPIO1_DIR            0xC0000000  /* SPI CS on 0, LED on 1 */
 186#define CONFIG_SYS_GPIO1_DAT            0xC0000000  /* Both are active LOW */
 187
 188/* TSEC */
 189#define CONFIG_SYS_TSEC1_OFFSET 0x24000
 190#define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 191#define CONFIG_SYS_TSEC2_OFFSET 0x25000
 192#define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 193
 194/* USB */
 195#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY       1 /* Use SYS board PHY */
 196
 197/*
 198 * General PCI
 199 * Addresses are mapped 1-1.
 200 */
 201#define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 202#define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 203#define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 204#define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 205#define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 206#define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 207#define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 208#define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 209#define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 210
 211#define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 212#define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 213#define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 214#define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 215#define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 216#define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 217#define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 218#define CONFIG_SYS_PCI2_IO_PHYS         0xE2100000
 219#define CONFIG_SYS_PCI2_IO_SIZE         0x00100000      /* 1M */
 220
 221#if defined(CONFIG_PCI)
 222
 223#define CONFIG_83XX_PCI_STREAMING
 224
 225#undef CONFIG_EEPRO100
 226#undef CONFIG_TULIP
 227
 228#if !defined(CONFIG_PCI_PNP)
 229        #define PCI_ENET0_IOADDR        0xFIXME
 230        #define PCI_ENET0_MEMADDR       0xFIXME
 231        #define PCI_IDSEL_NUMBER        0x0c    /* slot0->3(IDSEL)=12->15 */
 232#endif
 233
 234#undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 235#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
 236
 237#endif  /* CONFIG_PCI */
 238
 239/*
 240 * TSEC configuration
 241 */
 242
 243#if defined(CONFIG_TSEC_ENET)
 244
 245#define CONFIG_GMII             1       /* MII PHY management */
 246#define CONFIG_TSEC1            1
 247#define CONFIG_TSEC1_NAME       "TSEC0"
 248#define CONFIG_TSEC2            1
 249#define CONFIG_TSEC2_NAME       "TSEC1"
 250#define TSEC1_PHY_ADDR          0
 251#define TSEC2_PHY_ADDR          1
 252#define TSEC1_PHYIDX            0
 253#define TSEC2_PHYIDX            0
 254#define TSEC1_FLAGS             TSEC_GIGABIT
 255#define TSEC2_FLAGS             TSEC_GIGABIT
 256
 257/* Options are: TSEC[0-1] */
 258#define CONFIG_ETHPRIME         "TSEC0"
 259
 260#endif  /* CONFIG_TSEC_ENET */
 261
 262/*
 263 * Configure on-board RTC
 264 */
 265#define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
 266#define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68 */
 267
 268/*
 269 * Environment
 270 */
 271#ifndef CONFIG_SYS_RAMBOOT
 272/* Address and size of Redundant Environment Sector     */
 273#endif
 274
 275#define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 276#define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 277
 278/*
 279 * BOOTP options
 280 */
 281#define CONFIG_BOOTP_BOOTFILESIZE
 282
 283/*
 284 * Command line configuration.
 285 */
 286
 287#undef CONFIG_WATCHDOG                  /* watchdog disabled */
 288
 289/*
 290 * Miscellaneous configurable options
 291 */
 292#define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 293
 294/*
 295 * For booting Linux, the board info and command line data
 296 * have to be in the first 256 MB of memory, since this is
 297 * the maximum mapped by the Linux kernel during initialization.
 298 */
 299                                /* Initial Memory map for Linux*/
 300#define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 301#define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 302
 303#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 304
 305/*
 306 * System performance
 307 */
 308#define CONFIG_SYS_SCCR_TSEC1CM 1       /* TSEC1 clock mode (0-3) */
 309#define CONFIG_SYS_SCCR_TSEC2CM 1       /* TSEC2 & I2C0 clock mode (0-3) */
 310
 311/* System IO Config */
 312#define CONFIG_SYS_SICRH 0
 313#define CONFIG_SYS_SICRL SICRL_LDP_A
 314
 315#ifdef CONFIG_PCI
 316#define CONFIG_PCI_INDIRECT_BRIDGE
 317#endif
 318
 319#if defined(CONFIG_CMD_KGDB)
 320#define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 321#endif
 322
 323/*
 324 * Environment Configuration
 325 */
 326#define CONFIG_ENV_OVERWRITE
 327
 328#if defined(CONFIG_TSEC_ENET)
 329#define CONFIG_HAS_ETH1
 330#define CONFIG_HAS_ETH0
 331#endif
 332
 333#define CONFIG_HOSTNAME         "mpc8349emds"
 334#define CONFIG_ROOTPATH         "/nfsroot/rootfs"
 335#define CONFIG_BOOTFILE         "uImage"
 336
 337#define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 338
 339#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 340        "netdev=eth0\0"                                                 \
 341        "hostname=mpc8349emds\0"                                        \
 342        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 343                "nfsroot=${serverip}:${rootpath}\0"                     \
 344        "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 345        "addip=setenv bootargs ${bootargs} "                            \
 346                "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 347                ":${hostname}:${netdev}:off panic=1\0"                  \
 348        "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 349        "flash_nfs=run nfsargs addip addtty;"                           \
 350                "bootm ${kernel_addr}\0"                                \
 351        "flash_self=run ramargs addip addtty;"                          \
 352                "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 353        "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 354                "bootm\0"                                               \
 355        "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0"           \
 356        "update=protect off fe000000 fe03ffff; "                        \
 357                "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
 358        "upd=run load update\0"                                         \
 359        "fdtaddr=780000\0"                                              \
 360        "fdtfile=mpc834x_mds.dtb\0"                                     \
 361        ""
 362
 363#define CONFIG_NFSBOOTCOMMAND                                           \
 364        "setenv bootargs root=/dev/nfs rw "                             \
 365                "nfsroot=$serverip:$rootpath "                          \
 366                "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 367                                                        "$netdev:off "  \
 368                "console=$consoledev,$baudrate $othbootargs;"           \
 369        "tftp $loadaddr $bootfile;"                                     \
 370        "tftp $fdtaddr $fdtfile;"                                       \
 371        "bootm $loadaddr - $fdtaddr"
 372
 373#define CONFIG_RAMBOOTCOMMAND                                           \
 374        "setenv bootargs root=/dev/ram rw "                             \
 375                "console=$consoledev,$baudrate $othbootargs;"           \
 376        "tftp $ramdiskaddr $ramdiskfile;"                               \
 377        "tftp $loadaddr $bootfile;"                                     \
 378        "tftp $fdtaddr $fdtfile;"                                       \
 379        "bootm $loadaddr $ramdiskaddr $fdtaddr"
 380
 381#define CONFIG_BOOTCOMMAND      "run flash_self"
 382
 383#endif  /* __CONFIG_H */
 384