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12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15
16
17
18#define CONFIG_E300 1
19
20#undef CONFIG_SYS_DRAM_TEST
21#define CONFIG_SYS_MEMTEST_START 0x00000000
22#define CONFIG_SYS_MEMTEST_END 0x00100000
23
24
25
26
27#define CONFIG_DDR_ECC
28#define CONFIG_DDR_ECC_CMD
29#define CONFIG_SPD_EEPROM
30
31
32
33
34
35#define CONFIG_SYS_SPD_BUS_NUM 0
36#define SPD_EEPROM_ADDRESS1 0x52
37#define SPD_EEPROM_ADDRESS2 0x51
38#define CONFIG_DIMM_SLOTS_PER_CTLR 2
39#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
40#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
41#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
42
43
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50
51
52
53#undef CONFIG_DDR_32BIT
54
55#define CONFIG_SYS_SDRAM_BASE 0x00000000
56#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
57 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
58#undef CONFIG_DDR_2T_TIMING
59
60
61
62
63#define CONFIG_SYS_DDRCDR_VALUE 0x80080001
64
65#if defined(CONFIG_SPD_EEPROM)
66
67
68
69#define SPD_EEPROM_ADDRESS 0x51
70#else
71
72
73
74#define CONFIG_SYS_DDR_SIZE 256
75#if defined(CONFIG_DDR_II)
76#define CONFIG_SYS_DDRCDR 0x80080001
77#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
78#define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102
79#define CONFIG_SYS_DDR_TIMING_0 0x00220802
80#define CONFIG_SYS_DDR_TIMING_1 0x38357322
81#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
82#define CONFIG_SYS_DDR_TIMING_3 0x00000000
83#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
84#define CONFIG_SYS_DDR_MODE 0x47d00432
85#define CONFIG_SYS_DDR_MODE2 0x8000c000
86#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
87#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
88#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
89#else
90#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
91 | CSCONFIG_ROW_BIT_13 \
92 | CSCONFIG_COL_BIT_10)
93#define CONFIG_SYS_DDR_TIMING_1 0x36332321
94#define CONFIG_SYS_DDR_TIMING_2 0x00000800
95#define CONFIG_SYS_DDR_CONTROL 0xc2000000
96#define CONFIG_SYS_DDR_INTERVAL 0x04060100
97
98#if defined(CONFIG_DDR_32BIT)
99
100
101#define CONFIG_SYS_DDR_MODE 0x00000023
102#else
103
104
105#define CONFIG_SYS_DDR_MODE 0x00000022
106#endif
107#endif
108#endif
109
110
111
112
113#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000
114#define CONFIG_SYS_LBC_SDRAM_SIZE 64
115
116
117
118
119#define CONFIG_SYS_FLASH_BASE 0xFE000000
120#define CONFIG_SYS_FLASH_SIZE 32
121
122#define CONFIG_SYS_MAX_FLASH_BANKS 1
123#define CONFIG_SYS_MAX_FLASH_SECT 256
124
125#undef CONFIG_SYS_FLASH_CHECKSUM
126#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
127#define CONFIG_SYS_FLASH_WRITE_TOUT 500
128
129#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
130
131#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
132#define CONFIG_SYS_RAMBOOT
133#else
134#undef CONFIG_SYS_RAMBOOT
135#endif
136
137
138
139
140#define CONFIG_SYS_BCSR 0xE2400000
141
142#define CONFIG_SYS_INIT_RAM_LOCK 1
143#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
144#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
145
146#define CONFIG_SYS_GBL_DATA_OFFSET \
147 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
148#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
149
150#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
151#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
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188
189#define CONFIG_SYS_LBC_LSRT 0x32000000
190
191#define CONFIG_SYS_LBC_MRTPR 0x20000000
192
193#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
194 | LSDMR_BSMA1516 \
195 | LSDMR_RFCR8 \
196 | LSDMR_PRETOACT6 \
197 | LSDMR_ACTTORW3 \
198 | LSDMR_BL8 \
199 | LSDMR_WRC3 \
200 | LSDMR_CL3)
201
202
203
204
205#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
206#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
207#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
208#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
209#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
210
211
212
213
214#define CONFIG_SYS_NS16550_SERIAL
215#define CONFIG_SYS_NS16550_REG_SIZE 1
216#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
217
218#define CONFIG_SYS_BAUDRATE_TABLE \
219 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
220
221#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
222#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
223
224
225#define CONFIG_SYS_I2C
226#define CONFIG_SYS_I2C_FSL
227#define CONFIG_SYS_FSL_I2C_SPEED 400000
228#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
229#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
230#define CONFIG_SYS_FSL_I2C2_SPEED 400000
231#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
232#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
233#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
234
235
236#undef CONFIG_SOFT_SPI
237
238
239#define CONFIG_SYS_GPIO1_PRELIM
240#define CONFIG_SYS_GPIO1_DIR 0xC0000000
241#define CONFIG_SYS_GPIO1_DAT 0xC0000000
242
243
244#define CONFIG_SYS_TSEC1_OFFSET 0x24000
245#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
246#define CONFIG_SYS_TSEC2_OFFSET 0x25000
247#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
248
249
250#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1
251
252
253
254
255
256#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
257#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
258#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
259#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
260#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
261#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
262#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
263#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
264#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000
265
266#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
267#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
268#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000
269#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
270#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
271#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000
272#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
273#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
274#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000
275
276#if defined(CONFIG_PCI)
277
278#define CONFIG_83XX_PCI_STREAMING
279
280#undef CONFIG_EEPRO100
281#undef CONFIG_TULIP
282
283#if !defined(CONFIG_PCI_PNP)
284 #define PCI_ENET0_IOADDR 0xFIXME
285 #define PCI_ENET0_MEMADDR 0xFIXME
286 #define PCI_IDSEL_NUMBER 0x0c
287#endif
288
289#undef CONFIG_PCI_SCAN_SHOW
290#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957
291
292#endif
293
294
295
296
297
298#if defined(CONFIG_TSEC_ENET)
299
300#define CONFIG_GMII 1
301#define CONFIG_TSEC1 1
302#define CONFIG_TSEC1_NAME "TSEC0"
303#define CONFIG_TSEC2 1
304#define CONFIG_TSEC2_NAME "TSEC1"
305#define TSEC1_PHY_ADDR 0
306#define TSEC2_PHY_ADDR 1
307#define TSEC1_PHYIDX 0
308#define TSEC2_PHYIDX 0
309#define TSEC1_FLAGS TSEC_GIGABIT
310#define TSEC2_FLAGS TSEC_GIGABIT
311
312
313#define CONFIG_ETHPRIME "TSEC0"
314
315#endif
316
317
318
319
320#define CONFIG_RTC_DS1374
321#define CONFIG_SYS_I2C_RTC_ADDR 0x68
322
323
324
325
326#ifndef CONFIG_SYS_RAMBOOT
327
328#endif
329
330#define CONFIG_LOADS_ECHO 1
331#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
332
333
334
335
336#define CONFIG_BOOTP_BOOTFILESIZE
337
338
339
340
341
342#undef CONFIG_WATCHDOG
343
344
345
346
347#define CONFIG_SYS_LOAD_ADDR 0x2000000
348
349
350
351
352
353
354
355#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
356#define CONFIG_SYS_BOOTM_LEN (64 << 20)
357
358#define CONFIG_SYS_RCWH_PCIHOST 0x80000000
359
360
361
362
363#define CONFIG_SYS_SPCR_TSEC1EP 3
364#define CONFIG_SYS_SPCR_TSEC2EP 3
365#define CONFIG_SYS_SCCR_TSEC1CM 1
366#define CONFIG_SYS_SCCR_TSEC2CM 1
367
368
369#define CONFIG_SYS_SICRH 0
370#define CONFIG_SYS_SICRL SICRL_LDP_A
371
372#ifdef CONFIG_PCI
373#define CONFIG_PCI_INDIRECT_BRIDGE
374#endif
375
376#if defined(CONFIG_CMD_KGDB)
377#define CONFIG_KGDB_BAUDRATE 230400
378#endif
379
380
381
382
383#define CONFIG_ENV_OVERWRITE
384
385#if defined(CONFIG_TSEC_ENET)
386#define CONFIG_HAS_ETH1
387#define CONFIG_HAS_ETH0
388#endif
389
390#define CONFIG_HOSTNAME "mpc8349emds"
391#define CONFIG_ROOTPATH "/nfsroot/rootfs"
392#define CONFIG_BOOTFILE "uImage"
393
394#define CONFIG_LOADADDR 800000
395
396#define CONFIG_EXTRA_ENV_SETTINGS \
397 "netdev=eth0\0" \
398 "hostname=mpc8349emds\0" \
399 "nfsargs=setenv bootargs root=/dev/nfs rw " \
400 "nfsroot=${serverip}:${rootpath}\0" \
401 "ramargs=setenv bootargs root=/dev/ram rw\0" \
402 "addip=setenv bootargs ${bootargs} " \
403 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
404 ":${hostname}:${netdev}:off panic=1\0" \
405 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
406 "flash_nfs=run nfsargs addip addtty;" \
407 "bootm ${kernel_addr}\0" \
408 "flash_self=run ramargs addip addtty;" \
409 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
410 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
411 "bootm\0" \
412 "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
413 "update=protect off fe000000 fe03ffff; " \
414 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
415 "upd=run load update\0" \
416 "fdtaddr=780000\0" \
417 "fdtfile=mpc834x_mds.dtb\0" \
418 ""
419
420#define CONFIG_NFSBOOTCOMMAND \
421 "setenv bootargs root=/dev/nfs rw " \
422 "nfsroot=$serverip:$rootpath " \
423 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
424 "$netdev:off " \
425 "console=$consoledev,$baudrate $othbootargs;" \
426 "tftp $loadaddr $bootfile;" \
427 "tftp $fdtaddr $fdtfile;" \
428 "bootm $loadaddr - $fdtaddr"
429
430#define CONFIG_RAMBOOTCOMMAND \
431 "setenv bootargs root=/dev/ram rw " \
432 "console=$consoledev,$baudrate $othbootargs;" \
433 "tftp $ramdiskaddr $ramdiskfile;" \
434 "tftp $loadaddr $bootfile;" \
435 "tftp $fdtaddr $fdtfile;" \
436 "bootm $loadaddr $ramdiskaddr $fdtaddr"
437
438#define CONFIG_BOOTCOMMAND "run flash_self"
439
440#endif
441