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10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#include "../board/freescale/common/ics307_clk.h"
14
15#ifndef CONFIG_RESET_VECTOR_ADDRESS
16#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
17#endif
18
19#ifndef CONFIG_SYS_MONITOR_BASE
20#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
21#endif
22
23
24
25#define CONFIG_PCIE1 1
26#define CONFIG_PCIE2 1
27#define CONFIG_PCIE3 1
28#define CONFIG_FSL_PCI_INIT 1
29#define CONFIG_PCI_INDIRECT_BRIDGE 1
30#define CONFIG_SYS_PCI_64BIT 1
31
32#define CONFIG_ENV_OVERWRITE
33
34#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
35#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
36#define CONFIG_ICS307_REFCLK_HZ 33333000
37
38
39
40
41#define CONFIG_L2_CACHE
42#define CONFIG_BTB
43
44#define CONFIG_ENABLE_36BIT_PHYS 1
45
46#ifdef CONFIG_PHYS_64BIT
47#define CONFIG_ADDR_MAP 1
48#define CONFIG_SYS_NUM_ADDR_MAP 16
49#endif
50
51#define CONFIG_SYS_MEMTEST_START 0x00000000
52#define CONFIG_SYS_MEMTEST_END 0x7fffffff
53
54
55
56
57#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
58#ifdef CONFIG_PHYS_64BIT
59#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
60#else
61#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
62#endif
63#define CONFIG_SYS_L2_SIZE (512 << 10)
64#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
65
66#define CONFIG_SYS_CCSRBAR 0xffe00000
67#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
68
69#if defined(CONFIG_NAND_SPL)
70#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
71#endif
72
73
74#define CONFIG_VERY_BIG_RAM
75#define CONFIG_SPD_EEPROM
76#define CONFIG_DDR_SPD
77
78#define CONFIG_DDR_ECC
79#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
80#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
81
82#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
83#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
84
85#define CONFIG_DIMM_SLOTS_PER_CTLR 1
86#define CONFIG_CHIP_SELECTS_PER_CTRL 2
87
88
89#define CONFIG_SYS_SPD_BUS_NUM 1
90#define SPD_EEPROM_ADDRESS1 0x51
91#define SPD_EEPROM_ADDRESS2 0x52
92
93
94#define CONFIG_SYS_SDRAM_SIZE 512
95#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
96#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202
97#define CONFIG_SYS_DDR_TIMING_3 0x00020000
98#define CONFIG_SYS_DDR_TIMING_0 0x00260802
99#define CONFIG_SYS_DDR_TIMING_1 0x626b2634
100#define CONFIG_SYS_DDR_TIMING_2 0x062874cf
101#define CONFIG_SYS_DDR_MODE_1 0x00440462
102#define CONFIG_SYS_DDR_MODE_2 0x00000000
103#define CONFIG_SYS_DDR_INTERVAL 0x0c300100
104#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
105#define CONFIG_SYS_DDR_CLK_CTRL 0x00800000
106#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
107#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
108#define CONFIG_SYS_DDR_CONTROL 0xc3000008
109#define CONFIG_SYS_DDR_CONTROL2 0x24400000
110
111#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
112#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
113#define CONFIG_SYS_DDR_SBE 0x00010000
114
115
116
117
118#ifndef CONFIG_SPD_EEPROM
119#error ("CONFIG_SPD_EEPROM is required")
120#endif
121
122#undef CONFIG_CLOCKS_IN_MHZ
123
124
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135
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144
145
146
147#define CONFIG_SYS_FLASH_BASE 0xe0000000
148#ifdef CONFIG_PHYS_64BIT
149#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
150#else
151#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
152#endif
153
154#define CONFIG_FLASH_BR_PRELIM \
155 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
156#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
157
158#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
159#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
160
161#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
162#define CONFIG_SYS_FLASH_QUIET_TEST
163#define CONFIG_FLASH_SHOW_PROGRESS 45
164
165#define CONFIG_SYS_MAX_FLASH_BANKS 2
166#define CONFIG_SYS_MAX_FLASH_SECT 1024
167#undef CONFIG_SYS_FLASH_CHECKSUM
168#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
169#define CONFIG_SYS_FLASH_WRITE_TOUT 500
170
171#undef CONFIG_SYS_RAMBOOT
172
173#define CONFIG_SYS_FLASH_EMPTY_INFO
174#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
175
176#define CONFIG_HWCONFIG
177#define CONFIG_FSL_PIXIS 1
178#define PIXIS_BASE 0xffdf0000
179#ifdef CONFIG_PHYS_64BIT
180#define PIXIS_BASE_PHYS 0xfffdf0000ull
181#else
182#define PIXIS_BASE_PHYS PIXIS_BASE
183#endif
184
185#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
186#define CONFIG_SYS_OR3_PRELIM 0xffffeff7
187
188#define PIXIS_ID 0x0
189#define PIXIS_VER 0x1
190#define PIXIS_PVER 0x2
191#define PIXIS_CSR 0x3
192#define PIXIS_RST 0x4
193#define PIXIS_PWR 0x5
194#define PIXIS_AUX 0x6
195#define PIXIS_SPD 0x7
196#define PIXIS_AUX2 0x8
197#define PIXIS_VCTL 0x10
198#define PIXIS_VSTAT 0x11
199#define PIXIS_VCFGEN0 0x12
200#define PIXIS_VCFGEN1 0x13
201#define PIXIS_VCORE0 0x14
202#define PIXIS_VBOOT 0x16
203#define PIXIS_VBOOT_LBMAP 0xc0
204#define PIXIS_VBOOT_LBMAP_NOR0 0x00
205#define PIXIS_VBOOT_LBMAP_PJET 0x01
206#define PIXIS_VBOOT_LBMAP_NAND 0x02
207#define PIXIS_VBOOT_LBMAP_NOR1 0x03
208#define PIXIS_VSPEED0 0x17
209#define PIXIS_VSPEED1 0x18
210#define PIXIS_VSPEED2 0x19
211#define PIXIS_VSYSCLK0 0x1C
212#define PIXIS_VSYSCLK1 0x1D
213#define PIXIS_VSYSCLK2 0x1E
214#define PIXIS_VDDRCLK0 0x1F
215#define PIXIS_VDDRCLK1 0x20
216#define PIXIS_VDDRCLK2 0x21
217#define PIXIS_VWATCH 0x24
218#define PIXIS_LED 0x25
219
220#define PIXIS_SPD_SYSCLK_MASK 0x7
221
222
223#define PIXIS_VCLKH 0x19
224#define PIXIS_VCLKL 0x1A
225#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
226#define PIXIS_VSPEED2_TSEC1SER 0x8
227#define PIXIS_VSPEED2_TSEC2SER 0x4
228#define PIXIS_VSPEED2_TSEC3SER 0x2
229#define PIXIS_VSPEED2_TSEC4SER 0x1
230#define PIXIS_VCFGEN1_TSEC1SER 0x20
231#define PIXIS_VCFGEN1_TSEC2SER 0x20
232#define PIXIS_VCFGEN1_TSEC3SER 0x20
233#define PIXIS_VCFGEN1_TSEC4SER 0x20
234#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
235 | PIXIS_VSPEED2_TSEC2SER \
236 | PIXIS_VSPEED2_TSEC3SER \
237 | PIXIS_VSPEED2_TSEC4SER)
238#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
239 | PIXIS_VCFGEN1_TSEC2SER \
240 | PIXIS_VCFGEN1_TSEC3SER \
241 | PIXIS_VCFGEN1_TSEC4SER)
242
243#define CONFIG_SYS_INIT_RAM_LOCK 1
244#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
245#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
246
247#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
248#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
249
250#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
251#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
252
253#ifndef CONFIG_NAND_SPL
254#define CONFIG_SYS_NAND_BASE 0xffa00000
255#ifdef CONFIG_PHYS_64BIT
256#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
257#else
258#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
259#endif
260#else
261#define CONFIG_SYS_NAND_BASE 0xfff00000
262#ifdef CONFIG_PHYS_64BIT
263#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
264#else
265#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
266#endif
267#endif
268
269#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
270 CONFIG_SYS_NAND_BASE + 0x40000, \
271 CONFIG_SYS_NAND_BASE + 0x80000,\
272 CONFIG_SYS_NAND_BASE + 0xC0000}
273#define CONFIG_SYS_MAX_NAND_DEVICE 4
274#define CONFIG_NAND_FSL_ELBC 1
275#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
276#define CONFIG_SYS_NAND_MAX_OOBFREE 5
277#define CONFIG_SYS_NAND_MAX_ECCPOS 56
278
279
280#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
281#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
282#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
283#define CONFIG_SYS_NAND_U_BOOT_START \
284 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
285#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
286#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
287#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
288
289
290#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
291 | (2<<BR_DECC_SHIFT) \
292 | BR_PS_8 \
293 | BR_MS_FCM \
294 | BR_V)
295#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 \
296 | OR_FCM_PGS \
297 | OR_FCM_CSCT \
298 | OR_FCM_CST \
299 | OR_FCM_CHT \
300 | OR_FCM_SCY_1 \
301 | OR_FCM_TRLX \
302 | OR_FCM_EHTR)
303
304#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM
305#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM
306#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM
307#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM
308#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
309 | (2<<BR_DECC_SHIFT) \
310 | BR_PS_8 \
311 | BR_MS_FCM \
312 | BR_V)
313#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM
314#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
315 | (2<<BR_DECC_SHIFT) \
316 | BR_PS_8 \
317 | BR_MS_FCM \
318 | BR_V)
319#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM
320
321#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\
322 | (2<<BR_DECC_SHIFT) \
323 | BR_PS_8 \
324 | BR_MS_FCM \
325 | BR_V)
326#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM
327
328
329
330
331
332#define CONFIG_SYS_NS16550_SERIAL
333#define CONFIG_SYS_NS16550_REG_SIZE 1
334#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
335#ifdef CONFIG_NAND_SPL
336#define CONFIG_NS16550_MIN_FUNCTIONS
337#endif
338
339#define CONFIG_SYS_BAUDRATE_TABLE \
340 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
341
342#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
343#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
344
345
346#define CONFIG_SYS_I2C
347#define CONFIG_SYS_I2C_FSL
348#define CONFIG_SYS_FSL_I2C_SPEED 400000
349#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
350#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
351#define CONFIG_SYS_FSL_I2C2_SPEED 400000
352#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
353#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
354#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
355#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
356
357
358
359
360#define CONFIG_ID_EEPROM
361#ifdef CONFIG_ID_EEPROM
362#define CONFIG_SYS_I2C_EEPROM_NXID
363#endif
364#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
365#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
366#define CONFIG_SYS_EEPROM_BUS_NUM 1
367
368
369
370
371
372
373
374#define CONFIG_SYS_PCIE3_NAME "ULI"
375#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
376#ifdef CONFIG_PHYS_64BIT
377#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
378#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
379#else
380#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
381#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
382#endif
383#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000
384#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
385#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
386#ifdef CONFIG_PHYS_64BIT
387#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
388#else
389#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
390#endif
391#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
392
393
394#define CONFIG_SYS_PCIE2_NAME "Slot 1"
395#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
396#ifdef CONFIG_PHYS_64BIT
397#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
398#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
399#else
400#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
401#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
402#endif
403#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000
404#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
405#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
406#ifdef CONFIG_PHYS_64BIT
407#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
408#else
409#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
410#endif
411#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
412
413
414#define CONFIG_SYS_PCIE1_NAME "Slot 2"
415#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
416#ifdef CONFIG_PHYS_64BIT
417#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
418#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
419#else
420#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
421#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
422#endif
423#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
424#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
425#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
426#ifdef CONFIG_PHYS_64BIT
427#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
428#else
429#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
430#endif
431#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
432
433#if defined(CONFIG_PCI)
434
435
436#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
437
438
439
440#if defined(CONFIG_VIDEO)
441#define CONFIG_BIOSEMU
442#define CONFIG_ATI_RADEON_FB
443#define CONFIG_VIDEO_LOGO
444#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
445#endif
446
447#undef CONFIG_EEPRO100
448#undef CONFIG_TULIP
449
450#ifndef CONFIG_PCI_PNP
451 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
452 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
453 #define PCI_IDSEL_NUMBER 0x11
454#endif
455
456#define CONFIG_PCI_SCAN_SHOW
457
458#ifdef CONFIG_SCSI_AHCI
459#define CONFIG_SATA_ULI5288
460#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
461#define CONFIG_SYS_SCSI_MAX_LUN 1
462#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
463#endif
464
465#endif
466
467#if defined(CONFIG_TSEC_ENET)
468
469#define CONFIG_MII_DEFAULT_TSEC 1
470#define CONFIG_TSEC1 1
471#define CONFIG_TSEC1_NAME "eTSEC1"
472#define CONFIG_TSEC2 1
473#define CONFIG_TSEC2_NAME "eTSEC2"
474#define CONFIG_TSEC3 1
475#define CONFIG_TSEC3_NAME "eTSEC3"
476#define CONFIG_TSEC4 1
477#define CONFIG_TSEC4_NAME "eTSEC4"
478
479#define CONFIG_PIXIS_SGMII_CMD
480#define CONFIG_FSL_SGMII_RISER 1
481#define SGMII_RISER_PHY_OFFSET 0x1c
482
483#ifdef CONFIG_FSL_SGMII_RISER
484#define CONFIG_SYS_TBIPA_VALUE 0x10
485#endif
486
487#define TSEC1_PHY_ADDR 0
488#define TSEC2_PHY_ADDR 1
489#define TSEC3_PHY_ADDR 2
490#define TSEC4_PHY_ADDR 3
491
492#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
493#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
494#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
495#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
496
497#define TSEC1_PHYIDX 0
498#define TSEC2_PHYIDX 0
499#define TSEC3_PHYIDX 0
500#define TSEC4_PHYIDX 0
501
502#define CONFIG_ETHPRIME "eTSEC1"
503#endif
504
505
506
507
508
509#define CONFIG_LOADS_ECHO 1
510#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
511
512
513
514
515
516#ifdef CONFIG_USB_EHCI_HCD
517#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
518#define CONFIG_PCI_EHCI_DEVICE 0
519#endif
520
521#undef CONFIG_WATCHDOG
522
523
524
525
526#define CONFIG_SYS_LOAD_ADDR 0x2000000
527
528
529
530
531
532
533#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
534#define CONFIG_SYS_BOOTM_LEN (64 << 20)
535
536#if defined(CONFIG_CMD_KGDB)
537#define CONFIG_KGDB_BAUDRATE 230400
538#endif
539
540
541
542
543#if defined(CONFIG_TSEC_ENET)
544#define CONFIG_HAS_ETH0
545#define CONFIG_HAS_ETH1
546#define CONFIG_HAS_ETH2
547#define CONFIG_HAS_ETH3
548#endif
549
550#define CONFIG_IPADDR 192.168.1.254
551
552#define CONFIG_HOSTNAME "unknown"
553#define CONFIG_ROOTPATH "/opt/nfsroot"
554#define CONFIG_BOOTFILE "uImage"
555#define CONFIG_UBOOTPATH u-boot.bin
556
557#define CONFIG_SERVERIP 192.168.1.1
558#define CONFIG_GATEWAYIP 192.168.1.1
559#define CONFIG_NETMASK 255.255.255.0
560
561
562#define CONFIG_LOADADDR 1000000
563
564#define CONFIG_EXTRA_ENV_SETTINGS \
565"hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \
566"netdev=eth0\0" \
567"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
568"tftpflash=tftpboot $loadaddr $uboot; " \
569 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
570 " +$filesize; " \
571 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
572 " +$filesize; " \
573 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
574 " $filesize; " \
575 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
576 " +$filesize; " \
577 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
578 " $filesize\0" \
579"consoledev=ttyS0\0" \
580"ramdiskaddr=2000000\0" \
581"ramdiskfile=8572ds/ramdisk.uboot\0" \
582"fdtaddr=1e00000\0" \
583"fdtfile=8572ds/mpc8572ds.dtb\0" \
584"bdev=sda3\0"
585
586#define CONFIG_HDBOOT \
587 "setenv bootargs root=/dev/$bdev rw " \
588 "console=$consoledev,$baudrate $othbootargs;" \
589 "tftp $loadaddr $bootfile;" \
590 "tftp $fdtaddr $fdtfile;" \
591 "bootm $loadaddr - $fdtaddr"
592
593#define CONFIG_NFSBOOTCOMMAND \
594 "setenv bootargs root=/dev/nfs rw " \
595 "nfsroot=$serverip:$rootpath " \
596 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
597 "console=$consoledev,$baudrate $othbootargs;" \
598 "tftp $loadaddr $bootfile;" \
599 "tftp $fdtaddr $fdtfile;" \
600 "bootm $loadaddr - $fdtaddr"
601
602#define CONFIG_RAMBOOTCOMMAND \
603 "setenv bootargs root=/dev/ram rw " \
604 "console=$consoledev,$baudrate $othbootargs;" \
605 "tftp $ramdiskaddr $ramdiskfile;" \
606 "tftp $loadaddr $bootfile;" \
607 "tftp $fdtaddr $fdtfile;" \
608 "bootm $loadaddr $ramdiskaddr $fdtaddr"
609
610#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
611
612#endif
613