LXR uboot/include/configs/MPC8610HPCD.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Copyright 2007-2011 Freescale Semiconductor, Inc.
   4 */
   5
   6/*
   7 * MPC8610HPCD board configuration file
   8 */
   9
  10#ifndef __CONFIG_H
  11#define __CONFIG_H
  12
  13/* High Level Configuration Options */
  14#define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
  15
  16/* video */
  17#define CONFIG_FSL_DIU_FB
  18
  19#ifdef CONFIG_FSL_DIU_FB
  20#define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x2c000)
  21#define CONFIG_VIDEO_LOGO
  22#define CONFIG_VIDEO_BMP_LOGO
  23#endif
  24
  25#ifdef RUN_DIAG
  26#define CONFIG_SYS_DIAG_ADDR            0xff800000
  27#endif
  28
  29/*
  30 * virtual address to be used for temporary mappings.  There
  31 * should be 128k free at this VA.
  32 */
  33#define CONFIG_SYS_SCRATCH_VA   0xc0000000
  34
  35#define CONFIG_PCI1             1       /* PCI controller 1 */
  36#define CONFIG_PCIE1            1       /* PCIe 1 connected to ULI bridge */
  37#define CONFIG_PCIE2            1       /* PCIe 2 connected to slot */
  38#define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  39#define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  40#define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  41
  42#define CONFIG_ENV_OVERWRITE
  43#define CONFIG_INTERRUPTS               /* enable pci, srio, ddr interrupts */
  44
  45#define CONFIG_BAT_RW           1       /* Use common BAT rw code */
  46#define CONFIG_ALTIVEC          1
  47
  48/*
  49 * L2CR setup -- make sure this is right for your board!
  50 */
  51#define CONFIG_SYS_L2
  52#define L2_INIT         0
  53#define L2_ENABLE       (L2CR_L2E |0x00100000 )
  54
  55#ifndef CONFIG_SYS_CLK_FREQ
  56#define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  57#endif
  58
  59#define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  60#define CONFIG_SYS_MEMTEST_END          0x00400000
  61
  62/*
  63 * Base addresses -- Note these are effective addresses where the
  64 * actual resources get mapped (not physical addresses)
  65 */
  66#define CONFIG_SYS_CCSRBAR              0xe0000000      /* relocated CCSRBAR */
  67#define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  68
  69#define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  70#define CONFIG_SYS_CCSRBAR_PHYS_HIGH    0x0
  71#define CONFIG_SYS_CCSRBAR_PHYS         CONFIG_SYS_CCSRBAR_PHYS_LOW
  72
  73/* DDR Setup */
  74#define CONFIG_SPD_EEPROM               /* Use SPD for DDR */
  75#define CONFIG_DDR_SPD
  76
  77#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  78#define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  79
  80#define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
  81#define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  82#define CONFIG_SYS_MAX_DDR_BAT_SIZE     0x80000000      /* BAT mapping size */
  83#define CONFIG_VERY_BIG_RAM
  84
  85#define CONFIG_DIMM_SLOTS_PER_CTLR      1
  86#define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  87
  88#define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
  89
  90/* These are used when DDR doesn't use SPD.  */
  91#define CONFIG_SYS_SDRAM_SIZE   256             /* DDR is 256MB */
  92
  93#if 0 /* TODO */
  94#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
  95#define CONFIG_SYS_DDR_CS0_CONFIG       0x80010202      /* Enable, no interleaving */
  96#define CONFIG_SYS_DDR_TIMING_3 0x00000000
  97#define CONFIG_SYS_DDR_TIMING_0 0x00260802
  98#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
  99#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
 100#define CONFIG_SYS_DDR_MODE_1           0x00480432
 101#define CONFIG_SYS_DDR_MODE_2           0x00000000
 102#define CONFIG_SYS_DDR_INTERVAL 0x06180100
 103#define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 104#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
 105#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
 106#define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
 107#define CONFIG_SYS_DDR_CONTROL          0xe3008000      /* Type = DDR2 */
 108#define CONFIG_SYS_DDR_CONTROL2 0x04400010
 109
 110#define CONFIG_SYS_DDR_ERR_INT_EN       0x00000000
 111#define CONFIG_SYS_DDR_ERR_DIS          0x00000000
 112#define CONFIG_SYS_DDR_SBE              0x000f0000
 113
 114#endif
 115
 116#define CONFIG_ID_EEPROM
 117#define CONFIG_SYS_I2C_EEPROM_NXID
 118#define CONFIG_ID_EEPROM
 119#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
 120#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 121
 122#define CONFIG_SYS_FLASH_BASE           0xf0000000 /* start of FLASH 128M */
 123#define CONFIG_SYS_FLASH_BASE2          0xf8000000
 124
 125#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
 126
 127#define CONFIG_SYS_BR0_PRELIM           0xf8001001 /* port size 16bit */
 128#define CONFIG_SYS_OR0_PRELIM           0xf8006e65 /* 128MB NOR Flash*/
 129
 130#define CONFIG_SYS_BR1_PRELIM           0xf0001001 /* port size 16bit */
 131#define CONFIG_SYS_OR1_PRELIM           0xf8006e65 /* 128MB Promjet */
 132#if 0 /* TODO */
 133#define CONFIG_SYS_BR2_PRELIM           0xf0000000
 134#define CONFIG_SYS_OR2_PRELIM           0xf0000000 /* 256MB NAND Flash - bank 1 */
 135#endif
 136#define CONFIG_SYS_BR3_PRELIM           0xe8000801 /* port size 8bit */
 137#define CONFIG_SYS_OR3_PRELIM           0xfff06ff7 /* 1MB PIXIS area*/
 138
 139#define CONFIG_FSL_PIXIS        1       /* use common PIXIS code */
 140#define PIXIS_BASE      0xe8000000      /* PIXIS registers */
 141#define PIXIS_ID                0x0     /* Board ID at offset 0 */
 142#define PIXIS_VER               0x1     /* Board version at offset 1 */
 143#define PIXIS_PVER              0x2     /* PIXIS FPGA version at offset 2 */
 144#define PIXIS_RST               0x4     /* PIXIS Reset Control register */
 145#define PIXIS_AUX               0x6     /* PIXIS Auxiliary register; Scratch */
 146#define PIXIS_SPD               0x7     /* Register for SYSCLK speed */
 147#define PIXIS_BRDCFG0           0x8     /* PIXIS Board Configuration Register0*/
 148#define PIXIS_VCTL              0x10    /* VELA Control Register */
 149#define PIXIS_VCFGEN0           0x12    /* VELA Config Enable 0 */
 150#define PIXIS_VCFGEN1           0x13    /* VELA Config Enable 1 */
 151#define PIXIS_VBOOT             0x16    /* VELA VBOOT Register */
 152#define PIXIS_VSPEED0           0x17    /* VELA VSpeed 0 */
 153#define PIXIS_VSPEED1           0x18    /* VELA VSpeed 1 */
 154#define PIXIS_VCLKH             0x19    /* VELA VCLKH register */
 155#define PIXIS_VCLKL             0x1A    /* VELA VCLKL register */
 156#define CONFIG_SYS_PIXIS_VBOOT_MASK     0xC0    /* Reset altbank mask */
 157
 158#define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 159#define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 160
 161#undef  CONFIG_SYS_FLASH_CHECKSUM
 162#define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 163#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 164#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 165#define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000      /* early monitor loc */
 166
 167#define CONFIG_SYS_FLASH_EMPTY_INFO
 168
 169#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 170#define CONFIG_SYS_RAMBOOT
 171#else
 172#undef  CONFIG_SYS_RAMBOOT
 173#endif
 174
 175#if defined(CONFIG_SYS_RAMBOOT)
 176#undef CONFIG_SPD_EEPROM
 177#define CONFIG_SYS_SDRAM_SIZE   256
 178#endif
 179
 180#undef CONFIG_CLOCKS_IN_MHZ
 181
 182#define CONFIG_SYS_INIT_RAM_LOCK        1
 183#ifndef CONFIG_SYS_INIT_RAM_LOCK
 184#define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 185#else
 186#define CONFIG_SYS_INIT_RAM_ADDR        0xe4000000      /* Initial RAM address */
 187#endif
 188#define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 189
 190#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 191#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 192
 193#define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 KB for Mon */
 194#define CONFIG_SYS_MALLOC_LEN           (6 * 1024 * 1024)       /* Reserved for malloc */
 195
 196/* Serial Port */
 197#define CONFIG_SYS_NS16550_SERIAL
 198#define CONFIG_SYS_NS16550_REG_SIZE     1
 199#define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 200
 201#define CONFIG_SYS_BAUDRATE_TABLE \
 202        {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 203
 204#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 205#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 206
 207/* maximum size of the flat tree (8K) */
 208#define OF_FLAT_TREE_MAX_SIZE   8192
 209
 210/*
 211 * I2C
 212 */
 213#define CONFIG_SYS_I2C
 214#define CONFIG_SYS_I2C_FSL
 215#define CONFIG_SYS_FSL_I2C_SPEED        400000
 216#define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 217#define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 218#define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 219
 220/*
 221 * General PCI
 222 * Addresses are mapped 1-1.
 223 */
 224#define CONFIG_SYS_PCI1_MEM_BUS         0x80000000
 225#define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BUS
 226#define CONFIG_SYS_PCI1_MEM_VIRT        CONFIG_SYS_PCI1_MEM_BUS
 227#define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 228#define CONFIG_SYS_PCI1_IO_BUS  0x0000000
 229#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
 230#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
 231#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 232
 233/* controller 1, Base address 0xa000 */
 234#define CONFIG_SYS_PCIE1_NAME           "ULI"
 235#define CONFIG_SYS_PCIE1_MEM_BUS        0xa0000000
 236#define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BUS
 237#define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 238#define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 239#define CONFIG_SYS_PCIE1_IO_PHYS        0xe3000000
 240#define CONFIG_SYS_PCIE1_IO_SIZE        0x00100000      /* 1M */
 241
 242/* controller 2, Base Address 0x9000 */
 243#define CONFIG_SYS_PCIE2_NAME           "Slot 1"
 244#define CONFIG_SYS_PCIE2_MEM_BUS        0x90000000
 245#define CONFIG_SYS_PCIE2_MEM_PHYS       CONFIG_SYS_PCIE2_MEM_BUS
 246#define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 247#define CONFIG_SYS_PCIE2_IO_BUS         0x00000000      /* reuse mem LAW */
 248#define CONFIG_SYS_PCIE2_IO_PHYS        0xe2000000
 249#define CONFIG_SYS_PCIE2_IO_SIZE        0x00100000      /* 1M */
 250
 251#if defined(CONFIG_PCI)
 252
 253#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 254
 255#define CONFIG_ULI526X
 256
 257/************************************************************
 258 * USB support
 259 ************************************************************/
 260#define CONFIG_PCI_OHCI         1
 261#define CONFIG_USB_OHCI_NEW             1
 262#define CONFIG_SYS_USB_OHCI_SLOT_NAME   "ohci_pci"
 263#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
 264#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
 265
 266#if !defined(CONFIG_PCI_PNP)
 267#define PCI_ENET0_IOADDR        0xe0000000
 268#define PCI_ENET0_MEMADDR       0xe0000000
 269#define PCI_IDSEL_NUMBER        0x0c    /* slot0->3(IDSEL)=12->15 */
 270#endif
 271
 272#ifdef CONFIG_SCSI_AHCI
 273#define CONFIG_SATA_ULI5288
 274#define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 275#define CONFIG_SYS_SCSI_MAX_LUN 1
 276#define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 277#endif
 278
 279#endif  /* CONFIG_PCI */
 280
 281/*
 282 * BAT0         2G      Cacheable, non-guarded
 283 * 0x0000_0000  2G      DDR
 284 */
 285#define CONFIG_SYS_DBAT0L       (BATL_PP_RW)
 286#define CONFIG_SYS_IBAT0L       (BATL_PP_RW)
 287
 288/*
 289 * BAT1         1G      Cache-inhibited, guarded
 290 * 0x8000_0000  256M    PCI-1 Memory
 291 * 0xa000_0000  256M    PCI-Express 1 Memory
 292 * 0x9000_0000  256M    PCI-Express 2 Memory
 293 */
 294
 295#define CONFIG_SYS_DBAT1L       (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
 296                        | BATL_GUARDEDSTORAGE)
 297#define CONFIG_SYS_DBAT1U       (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
 298#define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 299#define CONFIG_SYS_IBAT1U       CONFIG_SYS_DBAT1U
 300
 301/*
 302 * BAT2         16M     Cache-inhibited, guarded
 303 * 0xe100_0000  1M      PCI-1 I/O
 304 */
 305
 306#define CONFIG_SYS_DBAT2L       (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
 307                        | BATL_GUARDEDSTORAGE)
 308#define CONFIG_SYS_DBAT2U       (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
 309#define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 310#define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 311
 312/*
 313 * BAT3         4M      Cache-inhibited, guarded
 314 * 0xe000_0000  4M      CCSR
 315 */
 316
 317#define CONFIG_SYS_DBAT3L       (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
 318                        | BATL_GUARDEDSTORAGE)
 319#define CONFIG_SYS_DBAT3U       (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
 320#define CONFIG_SYS_IBAT3L       (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
 321#define CONFIG_SYS_IBAT3U       CONFIG_SYS_DBAT3U
 322
 323#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
 324#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 325                                       | BATL_PP_RW | BATL_CACHEINHIBIT \
 326                                       | BATL_GUARDEDSTORAGE)
 327#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
 328                                       | BATU_BL_1M | BATU_VS | BATU_VP)
 329#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 330                                       | BATL_PP_RW | BATL_CACHEINHIBIT)
 331#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
 332#endif
 333
 334/*
 335 * BAT4         32M     Cache-inhibited, guarded
 336 * 0xe200_0000  1M      PCI-Express 2 I/O
 337 * 0xe300_0000  1M      PCI-Express 1 I/O
 338 */
 339
 340#define CONFIG_SYS_DBAT4L       (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
 341                        | BATL_GUARDEDSTORAGE)
 342#define CONFIG_SYS_DBAT4U       (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
 343#define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 344#define CONFIG_SYS_IBAT4U       CONFIG_SYS_DBAT4U
 345
 346/*
 347 * BAT5         128K    Cacheable, non-guarded
 348 * 0xe400_0000  128K    Init RAM for stack in the CPU DCache (no backing memory)
 349 */
 350#define CONFIG_SYS_DBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 351#define CONFIG_SYS_DBAT5U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 352#define CONFIG_SYS_IBAT5L       CONFIG_SYS_DBAT5L
 353#define CONFIG_SYS_IBAT5U       CONFIG_SYS_DBAT5U
 354
 355/*
 356 * BAT6         256M    Cache-inhibited, guarded
 357 * 0xf000_0000  256M    FLASH
 358 */
 359#define CONFIG_SYS_DBAT6L       (CONFIG_SYS_FLASH_BASE   | BATL_PP_RW | BATL_CACHEINHIBIT \
 360                        | BATL_GUARDEDSTORAGE)
 361#define CONFIG_SYS_DBAT6U       (CONFIG_SYS_FLASH_BASE   | BATU_BL_256M | BATU_VS | BATU_VP)
 362#define CONFIG_SYS_IBAT6L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
 363#define CONFIG_SYS_IBAT6U       CONFIG_SYS_DBAT6U
 364
 365/* Map the last 1M of flash where we're running from reset */
 366#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 367                                 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 368#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
 369#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 370                                 | BATL_MEMCOHERENCE)
 371#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
 372
 373/*
 374 * BAT7         4M      Cache-inhibited, guarded
 375 * 0xe800_0000  4M      PIXIS
 376 */
 377#define CONFIG_SYS_DBAT7L       (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
 378                        | BATL_GUARDEDSTORAGE)
 379#define CONFIG_SYS_DBAT7U       (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
 380#define CONFIG_SYS_IBAT7L       (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 381#define CONFIG_SYS_IBAT7U       CONFIG_SYS_DBAT7U
 382
 383/*
 384 * Environment
 385 */
 386
 387#define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 388#define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 389
 390/*
 391 * BOOTP options
 392 */
 393#define CONFIG_BOOTP_BOOTFILESIZE
 394
 395/*
 396 * Command line configuration.
 397 */
 398
 399#define CONFIG_WATCHDOG                 /* watchdog enabled */
 400#define CONFIG_SYS_WATCHDOG_FREQ        5000    /* Feed interval, 5s */
 401
 402/*
 403 * Miscellaneous configurable options
 404 */
 405#define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 406
 407/*
 408 * For booting Linux, the board info and command line data
 409 * have to be in the first 8 MB of memory, since this is
 410 * the maximum mapped by the Linux kernel during initialization.
 411 */
 412#define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Initial Memory map for Linux*/
 413#define CONFIG_SYS_BOOTM_LEN    (256 << 20)     /* Increase max gunzip size */
 414
 415#if defined(CONFIG_CMD_KGDB)
 416#define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 417#endif
 418
 419/*
 420 * Environment Configuration
 421 */
 422#define CONFIG_IPADDR           192.168.1.100
 423
 424#define CONFIG_HOSTNAME         "unknown"
 425#define CONFIG_ROOTPATH         "/opt/nfsroot"
 426#define CONFIG_BOOTFILE         "uImage"
 427#define CONFIG_UBOOTPATH        8610hpcd/u-boot.bin
 428
 429#define CONFIG_SERVERIP         192.168.1.1
 430#define CONFIG_GATEWAYIP        192.168.1.1
 431#define CONFIG_NETMASK          255.255.255.0
 432
 433/* default location for tftp and bootm */
 434#define CONFIG_LOADADDR         0x10000000
 435
 436#if defined(CONFIG_PCI1)
 437#define PCI_ENV \
 438 "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
 439        "echo e;md ${a}e00 9\0" \
 440 "pci1regs=setenv a e0008; run pcireg\0" \
 441 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
 442        "pci d.w $b.0 56 1\0" \
 443 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
 444        "pci w.w $b.0 56 ffff\0"        \
 445 "pci1err=setenv a e0008; run pcierr\0" \
 446 "pci1errc=setenv a e0008; run pcierrc\0"
 447#else
 448#define PCI_ENV ""
 449#endif
 450
 451#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2)
 452#define PCIE_ENV \
 453 "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
 454        "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
 455 "pcie1regs=setenv a e000a; run pciereg\0"      \
 456 "pcie2regs=setenv a e0009; run pciereg\0"      \
 457 "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\
 458        "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;"        \
 459        "pci d $b.0 130 1\0" \
 460 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\
 461        "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \
 462        "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0"            \
 463 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0"       \
 464 "pcie1err=setenv a e000a; run pcieerr\0"       \
 465 "pcie2err=setenv a e0009; run pcieerr\0"       \
 466 "pcie1errc=setenv a e000a; run pcieerrc\0"     \
 467 "pcie2errc=setenv a e0009; run pcieerrc\0"
 468#else
 469#define PCIE_ENV ""
 470#endif
 471
 472#define DMA_ENV \
 473 "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\
 474        "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \
 475 "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\
 476        "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \
 477 "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\
 478        "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \
 479 "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
 480        "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
 481
 482#ifdef ENV_DEBUG
 483#define CONFIG_EXTRA_ENV_SETTINGS                               \
 484"netdev=eth0\0"                                                 \
 485"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 486"tftpflash=tftpboot $loadaddr $uboot; "                         \
 487        "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 488                " +$filesize; " \
 489        "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 490                " +$filesize; " \
 491        "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 492                " $filesize; "  \
 493        "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 494                " +$filesize; " \
 495        "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 496                " $filesize\0"  \
 497"consoledev=ttyS0\0"                                            \
 498"ramdiskaddr=0x18000000\0"                                      \
 499"ramdiskfile=8610hpcd/ramdisk.uboot\0"                          \
 500"fdtaddr=0x17c00000\0"                                          \
 501"fdtfile=8610hpcd/mpc8610_hpcd.dtb\0"                           \
 502"bdev=sda3\0"                                   \
 503"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
 504"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
 505"maxcpus=1"     \
 506"eoi=mw e00400b0 0\0"                                           \
 507"iack=md e00400a0 1\0"                                          \
 508"ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
 509        "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
 510        "md ${a}f00 5\0" \
 511"ddr1regs=setenv a e0002; run ddrreg\0" \
 512"gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
 513        "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
 514        "md ${a}e60 1; md ${a}ef0 1d\0" \
 515"guregs=setenv a e00e0; run gureg\0" \
 516"mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
 517"mcmregs=setenv a e0001; run mcmreg\0" \
 518"diuregs=md e002c000 1d\0" \
 519"dium=mw e002c01c\0" \
 520"diuerr=md e002c014 1\0" \
 521"pmregs=md e00e1000 2b\0" \
 522"lawregs=md e0000c08 4b\0" \
 523"lbcregs=md e0005000 36\0" \
 524"dma0regs=md e0021100 12\0" \
 525"dma1regs=md e0021180 12\0" \
 526"dma2regs=md e0021200 12\0" \
 527"dma3regs=md e0021280 12\0" \
 528 PCI_ENV \
 529 PCIE_ENV \
 530 DMA_ENV
 531#else
 532#define CONFIG_EXTRA_ENV_SETTINGS                               \
 533        "netdev=eth0\0"                                         \
 534        "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 535        "consoledev=ttyS0\0"                                    \
 536        "ramdiskaddr=0x18000000\0"                              \
 537        "ramdiskfile=8610hpcd/ramdisk.uboot\0"                  \
 538        "fdtaddr=0x17c00000\0"                                  \
 539        "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0"                   \
 540        "bdev=sda3\0"
 541#endif
 542
 543#define CONFIG_NFSBOOTCOMMAND                                   \
 544 "setenv bootargs root=/dev/nfs rw "                            \
 545        "nfsroot=$serverip:$rootpath "                          \
 546        "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 547        "console=$consoledev,$baudrate $othbootargs;"           \
 548 "tftp $loadaddr $bootfile;"                                    \
 549 "tftp $fdtaddr $fdtfile;"                                      \
 550 "bootm $loadaddr - $fdtaddr"
 551
 552#define CONFIG_RAMBOOTCOMMAND \
 553 "setenv bootargs root=/dev/ram rw "                            \
 554        "console=$consoledev,$baudrate $othbootargs;"           \
 555 "tftp $ramdiskaddr $ramdiskfile;"                              \
 556 "tftp $loadaddr $bootfile;"                                    \
 557 "tftp $fdtaddr $fdtfile;"                                      \
 558 "bootm $loadaddr $ramdiskaddr $fdtaddr"
 559
 560#define CONFIG_BOOTCOMMAND              \
 561 "setenv bootargs root=/dev/$bdev rw "  \
 562        "console=$consoledev,$baudrate $othbootargs;"   \
 563 "tftp $loadaddr $bootfile;"            \
 564 "tftp $fdtaddr $fdtfile;"              \
 565 "bootm $loadaddr - $fdtaddr"
 566
 567#endif  /* __CONFIG_H */
 568