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23#ifndef __CONFIG_H
24#define __CONFIG_H
25
26
27
28
29
30#ifdef CONFIG_RAMBOOT_PBL
31#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
32#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
33#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
34#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
35#endif
36
37
38#define CONFIG_SYS_BOOK3E_HV
39
40
41#define CONFIG_DEEP_SLEEP
42
43#ifndef CONFIG_RESET_VECTOR_ADDRESS
44#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
45#endif
46
47#define CONFIG_SYS_FSL_CPC
48#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
49#define CONFIG_PCI_INDIRECT_BRIDGE
50#define CONFIG_PCIE1
51#define CONFIG_PCIE2
52#define CONFIG_PCIE3
53#define CONFIG_PCIE4
54
55#define CONFIG_FSL_PCI_INIT
56#define CONFIG_SYS_PCI_64BIT
57
58#define CONFIG_ENV_OVERWRITE
59
60#ifdef CONFIG_MTD_NOR_FLASH
61#if defined(CONFIG_SPIFLASH)
62#elif defined(CONFIG_SDCARD)
63#define CONFIG_SYS_MMC_ENV_DEV 0
64#endif
65#endif
66
67#ifndef __ASSEMBLY__
68unsigned long get_board_sys_clk(void);
69unsigned long get_board_ddr_clk(void);
70#endif
71
72#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
73#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
74
75
76
77
78#define CONFIG_SYS_CACHE_STASHING
79#define CONFIG_BACKSIDE_L2_CACHE
80#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
81#define CONFIG_BTB
82#define CONFIG_DDR_ECC
83#ifdef CONFIG_DDR_ECC
84#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
85#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
86#endif
87
88#define CONFIG_ENABLE_36BIT_PHYS
89
90#define CONFIG_ADDR_MAP
91#define CONFIG_SYS_NUM_ADDR_MAP 64
92
93#define CONFIG_SYS_MEMTEST_START 0x00200000
94#define CONFIG_SYS_MEMTEST_END 0x00400000
95
96
97
98
99#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
100
101#define CONFIG_SYS_DCSRBAR 0xf0000000
102#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
103
104
105#define CONFIG_ID_EEPROM
106#define CONFIG_SYS_I2C_EEPROM_NXID
107#define CONFIG_SYS_EEPROM_BUS_NUM 0
108#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
109#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
110#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
111#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
112
113
114
115
116#define CONFIG_VERY_BIG_RAM
117#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
118#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
119
120#define CONFIG_DIMM_SLOTS_PER_CTLR 1
121#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
122
123#define CONFIG_DDR_SPD
124
125#define CONFIG_SYS_SPD_BUS_NUM 0
126#define SPD_EEPROM_ADDRESS 0x51
127
128#define CONFIG_SYS_SDRAM_SIZE 4096
129
130
131
132
133#define CONFIG_SYS_FLASH_BASE 0xe0000000
134#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
135
136#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
137#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
138 + 0x8000000) | \
139 CSPR_PORT_SIZE_16 | \
140 CSPR_MSEL_NOR | \
141 CSPR_V)
142#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
143#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
144 CSPR_PORT_SIZE_16 | \
145 CSPR_MSEL_NOR | \
146 CSPR_V)
147#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
148
149
150
151
152#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
153
154
155#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
156#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
157 FTIM0_NOR_TEADC(0x5) | \
158 FTIM0_NOR_TEAHC(0x5))
159#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
160 FTIM1_NOR_TRAD_NOR(0x1A) |\
161 FTIM1_NOR_TSEQRAD_NOR(0x13))
162#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
163 FTIM2_NOR_TCH(0x4) | \
164 FTIM2_NOR_TWPH(0x0E) | \
165 FTIM2_NOR_TWP(0x1c))
166#define CONFIG_SYS_NOR_FTIM3 0x0
167
168#define CONFIG_SYS_FLASH_QUIET_TEST
169#define CONFIG_FLASH_SHOW_PROGRESS 45
170
171#define CONFIG_SYS_MAX_FLASH_BANKS 2
172#define CONFIG_SYS_MAX_FLASH_SECT 1024
173#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
174#define CONFIG_SYS_FLASH_WRITE_TOUT 500
175
176#define CONFIG_SYS_FLASH_EMPTY_INFO
177#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
178 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
179#define CONFIG_FSL_QIXIS
180#define QIXIS_BASE 0xffdf0000
181#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
182#define QIXIS_LBMAP_SWITCH 0x06
183#define QIXIS_LBMAP_MASK 0x0f
184#define QIXIS_LBMAP_SHIFT 0
185#define QIXIS_LBMAP_DFLTBANK 0x00
186#define QIXIS_LBMAP_ALTBANK 0x04
187#define QIXIS_RST_CTL_RESET 0x31
188#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
189#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
190#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
191#define QIXIS_RST_FORCE_MEM 0x01
192
193#define CONFIG_SYS_CSPR3_EXT (0xf)
194#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
195 | CSPR_PORT_SIZE_8 \
196 | CSPR_MSEL_GPCM \
197 | CSPR_V)
198#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
199#define CONFIG_SYS_CSOR3 0x0
200
201#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
202 FTIM0_GPCM_TEADC(0x0e) | \
203 FTIM0_GPCM_TEAHC(0x0e))
204#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
205 FTIM1_GPCM_TRAD(0x3f))
206#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
207 FTIM2_GPCM_TCH(0x8) | \
208 FTIM2_GPCM_TWP(0x1f))
209#define CONFIG_SYS_CS3_FTIM3 0x0
210
211#define CONFIG_NAND_FSL_IFC
212#define CONFIG_SYS_NAND_BASE 0xff800000
213#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
214
215#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
216#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
217 | CSPR_PORT_SIZE_8 \
218 | CSPR_MSEL_NAND \
219 | CSPR_V)
220#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
221
222#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \
223 | CSOR_NAND_ECC_DEC_EN \
224 | CSOR_NAND_ECC_MODE_4 \
225 | CSOR_NAND_RAL_3 \
226 | CSOR_NAND_PGS_2K \
227 | CSOR_NAND_SPRZ_64 \
228 | CSOR_NAND_PB(64))
229
230#define CONFIG_SYS_NAND_ONFI_DETECTION
231
232
233#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
234 FTIM0_NAND_TWP(0x18) | \
235 FTIM0_NAND_TWCHT(0x07) | \
236 FTIM0_NAND_TWH(0x0a))
237#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
238 FTIM1_NAND_TWBE(0x39) | \
239 FTIM1_NAND_TRR(0x0e) | \
240 FTIM1_NAND_TRP(0x18))
241#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
242 FTIM2_NAND_TREH(0x0a) | \
243 FTIM2_NAND_TWHRE(0x1e))
244#define CONFIG_SYS_NAND_FTIM3 0x0
245
246#define CONFIG_SYS_NAND_DDR_LAW 11
247#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
248#define CONFIG_SYS_MAX_NAND_DEVICE 1
249
250#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
251
252#if defined(CONFIG_MTD_RAW_NAND)
253#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
254#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
255#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
256#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
257#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
258#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
259#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
260#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
261#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
262#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
263#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
264#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
265#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
266#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
267#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
268#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
269#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
270#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
271#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
272#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
273#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
274#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
275#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
276#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
277#else
278#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
279#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
280#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
281#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
282#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
283#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
284#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
285#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
286#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
287#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
288#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
289#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
290#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
291#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
292#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
293#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
294#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
295#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
296#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
297#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
298#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
299#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
300#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
301#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
302#endif
303
304#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
305
306#if defined(CONFIG_RAMBOOT_PBL)
307#define CONFIG_SYS_RAMBOOT
308#endif
309
310#define CONFIG_HWCONFIG
311
312
313#define CONFIG_L1_INIT_RAM
314#define CONFIG_SYS_INIT_RAM_LOCK
315#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000
316#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
317#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
318
319#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
320 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
321 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
322#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
323
324#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
325 GENERATED_GBL_DATA_SIZE)
326#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
327
328#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
329#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
330
331
332
333
334
335#define CONFIG_SYS_NS16550_SERIAL
336#define CONFIG_SYS_NS16550_REG_SIZE 1
337#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
338
339#define CONFIG_SYS_BAUDRATE_TABLE \
340 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
341
342#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
343#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
344#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
345#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
346
347
348#define CONFIG_FSL_DIU_FB
349#ifdef CONFIG_FSL_DIU_FB
350#define CONFIG_FSL_DIU_CH7301
351#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
352#define CONFIG_VIDEO_LOGO
353#define CONFIG_VIDEO_BMP_LOGO
354#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
355
356
357
358
359#undef CONFIG_SYS_FLASH_EMPTY_INFO
360#endif
361
362
363#define CONFIG_SYS_I2C
364#define CONFIG_SYS_I2C_FSL
365#define CONFIG_SYS_FSL_I2C_SPEED 50000
366#define CONFIG_SYS_FSL_I2C2_SPEED 50000
367#define CONFIG_SYS_FSL_I2C3_SPEED 50000
368#define CONFIG_SYS_FSL_I2C4_SPEED 50000
369#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
370#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
371#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
372#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
373#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
374#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
375#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
376#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
377
378#define I2C_MUX_PCA_ADDR 0x77
379#define I2C_MUX_PCA_ADDR_PRI 0x77
380
381
382#define I2C_MUX_CH_DEFAULT 0x8
383#define I2C_MUX_CH_DIU 0xC
384
385
386#define CONFIG_SYS_I2C_LDI_ADDR 0x38
387#define CONFIG_SYS_I2C_DVI_ADDR 0x75
388
389
390
391
392#define RTC
393#define CONFIG_RTC_DS3231 1
394#define CONFIG_SYS_I2C_RTC_ADDR 0x68
395
396
397
398
399
400
401
402
403
404
405#ifdef CONFIG_PCI
406
407#ifdef CONFIG_PCIE1
408#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
409#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
410#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
411#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
412#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
413#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
414#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
415#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
416#endif
417
418
419#ifdef CONFIG_PCIE2
420#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
421#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
422#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
423#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
424#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
425#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
426#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
427#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
428#endif
429
430
431#ifdef CONFIG_PCIE3
432#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
433#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
434#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
435#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000
436#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
437#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
438#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
439#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
440#endif
441
442
443#ifdef CONFIG_PCIE4
444#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
445#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
446#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
447#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000
448#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
449#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
450#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
451#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000
452#endif
453
454#define CONFIG_PCI_SCAN_SHOW
455#endif
456
457
458#define CONFIG_FSL_SATA_V2
459#ifdef CONFIG_FSL_SATA_V2
460#define CONFIG_SYS_SATA_MAX_DEVICE 2
461#define CONFIG_SATA1
462#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
463#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
464#define CONFIG_SATA2
465#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
466#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
467
468#define CONFIG_LBA48
469#endif
470
471
472
473
474#define CONFIG_HAS_FSL_DR_USB
475
476#ifdef CONFIG_HAS_FSL_DR_USB
477#ifdef CONFIG_USB_EHCI_HCD
478#define CONFIG_USB_EHCI_FSL
479#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
480#endif
481#endif
482
483#ifdef CONFIG_MMC
484#define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
485#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
486#define CONFIG_FSL_ESDHC_ADAPTER_IDENT
487#endif
488
489
490#ifndef CONFIG_NOBQFMAN
491#define CONFIG_SYS_BMAN_NUM_PORTALS 10
492#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
493#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
494#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
495#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
496#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
497#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
498#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
499#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
500 CONFIG_SYS_BMAN_CENA_SIZE)
501#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
502#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
503#define CONFIG_SYS_QMAN_NUM_PORTALS 10
504#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
505#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
506#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
507#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
508#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
509#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
510#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
511#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
512 CONFIG_SYS_QMAN_CENA_SIZE)
513#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
514#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
515
516#define CONFIG_SYS_DPAA_FMAN
517#define CONFIG_SYS_DPAA_PME
518
519
520#if defined(CONFIG_SPIFLASH)
521
522
523
524
525#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
526#elif defined(CONFIG_SDCARD)
527
528
529
530
531
532#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
533#elif defined(CONFIG_MTD_RAW_NAND)
534#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
535#else
536#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
537#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
538#endif
539#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
540#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
541#endif
542
543#ifdef CONFIG_SYS_DPAA_FMAN
544#define CONFIG_PHYLIB_10G
545#define CONFIG_PHY_VITESSE
546#define CONFIG_PHY_REALTEK
547#define CONFIG_PHY_TERANETICS
548#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
549#define SGMII_CARD_PORT2_PHY_ADDR 0x10
550#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
551#define SGMII_CARD_PORT4_PHY_ADDR 0x11
552#endif
553
554#ifdef CONFIG_FMAN_ENET
555#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01
556#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02
557
558#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
559#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
560#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
561#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
562
563#define CONFIG_ETHPRIME "FM1@DTSEC1"
564#endif
565
566
567#define CONFIG_VSC9953
568#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14
569#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18
570
571
572
573
574
575
576
577
578#define CONFIG_LOADS_ECHO
579#define CONFIG_SYS_LOADS_BAUD_CHANGE
580
581
582
583
584#define CONFIG_SYS_LOAD_ADDR 0x2000000
585
586
587
588
589
590
591#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
592#define CONFIG_SYS_BOOTM_LEN (64 << 20)
593
594#ifdef CONFIG_CMD_KGDB
595#define CONFIG_KGDB_BAUDRATE 230400
596#endif
597
598
599
600
601#define CONFIG_ROOTPATH "/opt/nfsroot"
602#define CONFIG_BOOTFILE "uImage"
603#define CONFIG_UBOOTPATH "u-boot.bin"
604
605
606#define CONFIG_LOADADDR 1000000
607
608#define __USB_PHY_TYPE utmi
609
610#define CONFIG_EXTRA_ENV_SETTINGS \
611 "hwconfig=fsl_ddr:bank_intlv=auto;" \
612 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
613 "netdev=eth0\0" \
614 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
615 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
616 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
617 "tftpflash=tftpboot $loadaddr $uboot && " \
618 "protect off $ubootaddr +$filesize && " \
619 "erase $ubootaddr +$filesize && " \
620 "cp.b $loadaddr $ubootaddr $filesize && " \
621 "protect on $ubootaddr +$filesize && " \
622 "cmp.b $loadaddr $ubootaddr $filesize\0" \
623 "consoledev=ttyS0\0" \
624 "ramdiskaddr=2000000\0" \
625 "ramdiskfile=t1040qds/ramdisk.uboot\0" \
626 "fdtaddr=1e00000\0" \
627 "fdtfile=t1040qds/t1040qds.dtb\0" \
628 "bdev=sda3\0"
629
630#define CONFIG_LINUX \
631 "setenv bootargs root=/dev/ram rw " \
632 "console=$consoledev,$baudrate $othbootargs;" \
633 "setenv ramdiskaddr 0x02000000;" \
634 "setenv fdtaddr 0x00c00000;" \
635 "setenv loadaddr 0x1000000;" \
636 "bootm $loadaddr $ramdiskaddr $fdtaddr"
637
638#define CONFIG_HDBOOT \
639 "setenv bootargs root=/dev/$bdev rw " \
640 "console=$consoledev,$baudrate $othbootargs;" \
641 "tftp $loadaddr $bootfile;" \
642 "tftp $fdtaddr $fdtfile;" \
643 "bootm $loadaddr - $fdtaddr"
644
645#define CONFIG_NFSBOOTCOMMAND \
646 "setenv bootargs root=/dev/nfs rw " \
647 "nfsroot=$serverip:$rootpath " \
648 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
649 "console=$consoledev,$baudrate $othbootargs;" \
650 "tftp $loadaddr $bootfile;" \
651 "tftp $fdtaddr $fdtfile;" \
652 "bootm $loadaddr - $fdtaddr"
653
654#define CONFIG_RAMBOOTCOMMAND \
655 "setenv bootargs root=/dev/ram rw " \
656 "console=$consoledev,$baudrate $othbootargs;" \
657 "tftp $ramdiskaddr $ramdiskfile;" \
658 "tftp $loadaddr $bootfile;" \
659 "tftp $fdtaddr $fdtfile;" \
660 "bootm $loadaddr $ramdiskaddr $fdtaddr"
661
662#define CONFIG_BOOTCOMMAND CONFIG_LINUX
663
664#include <asm/fsl_secure_boot.h>
665
666#endif
667