1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2007-2008 4 * Stelian Pop <stelian@popies.net> 5 * Lead Tech Design <www.leadtechdesign.com> 6 * 7 * Configuation settings for the AT91SAM9263EK board. 8 */ 9 10#ifndef __CONFIG_H 11#define __CONFIG_H 12 13/* 14 * SoC must be defined first, before hardware.h is included. 15 * In this case SoC is defined in boards.cfg. 16 */ 17#include <asm/hardware.h> 18 19/* ARM asynchronous clock */ 20#define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ 21#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 22 23#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 24#define CONFIG_SETUP_MEMORY_TAGS 1 25#define CONFIG_INITRD_TAG 1 26 27#ifndef CONFIG_SYS_USE_BOOT_NORFLASH 28#define CONFIG_SKIP_LOWLEVEL_INIT 29#else 30#define CONFIG_SYS_USE_NORFLASH 31#endif 32 33/* 34 * Hardware drivers 35 */ 36#define CONFIG_ATMEL_LEGACY 37 38/* LCD */ 39#define LCD_BPP LCD_COLOR8 40#define CONFIG_LCD_LOGO 1 41#undef LCD_TEST_PATTERN 42#define CONFIG_LCD_INFO 1 43#define CONFIG_LCD_INFO_BELOW_LOGO 1 44#define CONFIG_ATMEL_LCD 1 45#define CONFIG_ATMEL_LCD_BGR555 1 46 47/* 48 * BOOTP options 49 */ 50#define CONFIG_BOOTP_BOOTFILESIZE 1 51 52/* SDRAM */ 53#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 54#define CONFIG_SYS_SDRAM_SIZE 0x04000000 55 56#define CONFIG_SYS_INIT_SP_ADDR \ 57 (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) 58 59/* NOR flash, if populated */ 60#ifdef CONFIG_SYS_USE_NORFLASH 61#define PHYS_FLASH_1 0x10000000 62#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 63#define CONFIG_SYS_MAX_FLASH_SECT 256 64#define CONFIG_SYS_MAX_FLASH_BANKS 1 65 66#define CONFIG_SYS_MONITOR_SEC 1:0-3 67#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 68#define CONFIG_SYS_MONITOR_LEN (256 << 10) 69 70/* Address and size of Primary Environment Sector */ 71 72#define CONFIG_EXTRA_ENV_SETTINGS \ 73 "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ 74 "update=" \ 75 "protect off ${monitor_base} +${filesize};" \ 76 "erase ${monitor_base} +${filesize};" \ 77 "cp.b ${fileaddr} ${monitor_base} ${filesize};" \ 78 "protect on ${monitor_base} +${filesize}\0" 79 80#ifndef CONFIG_SKIP_LOWLEVEL_INIT 81#define MASTER_PLL_MUL 171 82#define MASTER_PLL_DIV 14 83#define MASTER_PLL_OUT 3 84 85/* clocks */ 86#define CONFIG_SYS_MOR_VAL \ 87 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) 88#define CONFIG_SYS_PLLAR_VAL \ 89 (AT91_PMC_PLLAR_29 | \ 90 AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ 91 AT91_PMC_PLLXR_PLLCOUNT(63) | \ 92 AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ 93 AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) 94 95/* PCK/2 = MCK Master Clock from PLLA */ 96#define CONFIG_SYS_MCKR1_VAL \ 97 (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ 98 AT91_PMC_MCKR_MDIV_2) 99 100/* PCK/2 = MCK Master Clock from PLLA */ 101#define CONFIG_SYS_MCKR2_VAL \ 102 (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ 103 AT91_PMC_MCKR_MDIV_2) 104 105/* define PDC[31:16] as DATA[31:16] */ 106#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 107/* no pull-up for D[31:16] */ 108#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 109/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ 110#define CONFIG_SYS_MATRIX_EBICSA_VAL \ 111 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ 112 AT91_MATRIX_CSA_EBI_CS1A) 113 114/* SDRAM */ 115/* SDRAMC_MR Mode register */ 116#define CONFIG_SYS_SDRC_MR_VAL1 0 117/* SDRAMC_TR - Refresh Timer register */ 118#define CONFIG_SYS_SDRC_TR_VAL1 0x13C 119/* SDRAMC_CR - Configuration register*/ 120#define CONFIG_SYS_SDRC_CR_VAL \ 121 (AT91_SDRAMC_NC_9 | \ 122 AT91_SDRAMC_NR_13 | \ 123 AT91_SDRAMC_NB_4 | \ 124 AT91_SDRAMC_CAS_3 | \ 125 AT91_SDRAMC_DBW_32 | \ 126 (1 << 8) | /* Write Recovery Delay */ \ 127 (7 << 12) | /* Row Cycle Delay */ \ 128 (2 << 16) | /* Row Precharge Delay */ \ 129 (2 << 20) | /* Row to Column Delay */ \ 130 (5 << 24) | /* Active to Precharge Delay */ \ 131 (1 << 28)) /* Exit Self Refresh to Active Delay */ 132 133/* Memory Device Register -> SDRAM */ 134#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM 135#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE 136#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ 137#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH 138#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ 139#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ 140#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ 141#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ 142#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ 143#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ 144#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ 145#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ 146#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR 147#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ 148#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL 149#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ 150#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ 151#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ 152 153/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ 154#define CONFIG_SYS_SMC0_SETUP0_VAL \ 155 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ 156 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) 157#define CONFIG_SYS_SMC0_PULSE0_VAL \ 158 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ 159 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) 160#define CONFIG_SYS_SMC0_CYCLE0_VAL \ 161 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) 162#define CONFIG_SYS_SMC0_MODE0_VAL \ 163 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ 164 AT91_SMC_MODE_DBW_16 | \ 165 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) 166 167/* user reset enable */ 168#define CONFIG_SYS_RSTC_RMR_VAL \ 169 (AT91_RSTC_KEY | \ 170 AT91_RSTC_MR_URSTEN | \ 171 AT91_RSTC_MR_ERSTL(15)) 172 173/* Disable Watchdog */ 174#define CONFIG_SYS_WDTC_WDMR_VAL \ 175 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ 176 AT91_WDT_MR_WDV(0xfff) | \ 177 AT91_WDT_MR_WDDIS | \ 178 AT91_WDT_MR_WDD(0xfff)) 179 180#endif 181#endif 182 183/* NAND flash */ 184#ifdef CONFIG_CMD_NAND 185#define CONFIG_SYS_MAX_NAND_DEVICE 1 186#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 187#define CONFIG_SYS_NAND_DBW_8 1 188/* our ALE is AD21 */ 189#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 190/* our CLE is AD22 */ 191#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 192#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 193#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 194#endif 195 196/* Ethernet */ 197#define CONFIG_RESET_PHY_R 1 198#define CONFIG_AT91_WANTS_COMMON_PHY 199 200/* USB */ 201#define CONFIG_USB_ATMEL 202#define CONFIG_USB_ATMEL_CLK_SEL_PLLB 203#define CONFIG_USB_OHCI_NEW 1 204#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 205#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ 206#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" 207#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 208 209#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 210 211#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 212#define CONFIG_SYS_MEMTEST_END 0x23e00000 213 214#ifdef CONFIG_SYS_USE_DATAFLASH 215 216/* bootstrap + u-boot + env + linux in dataflash on CS0 */ 217#define CONFIG_BOOTCOMMAND "sf probe 0; " \ 218 "sf read 0x22000000 0x84000 0x294000; " \ 219 "bootm 0x22000000" 220 221#elif CONFIG_SYS_USE_NANDFLASH 222 223/* bootstrap + u-boot + env + linux in nandflash */ 224#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" 225#endif 226 227/* 228 * Size of malloc() pool 229 */ 230#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) 231 232#endif 233