LXR uboot/include/configs/at91sam9m10g45ek.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * (C) Copyright 2007-2008
   4 * Stelian Pop <stelian@popies.net>
   5 * Lead Tech Design <www.leadtechdesign.com>
   6 *
   7 * Configuation settings for the AT91SAM9M10G45EK board(and AT91SAM9G45EKES).
   8 */
   9
  10#ifndef __CONFIG_H
  11#define __CONFIG_H
  12
  13#define CONFIG_ATMEL_LEGACY             /* required until (g)pio is fixed */
  14
  15/* ARM asynchronous clock */
  16#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
  17#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
  18
  19#define CONFIG_AT91SAM9M10G45EK
  20
  21#define CONFIG_CMDLINE_TAG              /* enable passing of ATAGs      */
  22#define CONFIG_SETUP_MEMORY_TAGS
  23#define CONFIG_INITRD_TAG
  24#define CONFIG_SKIP_LOWLEVEL_INIT
  25
  26/* general purpose I/O */
  27#define CONFIG_ATMEL_LEGACY             /* required until (g)pio is fixed */
  28
  29/* LCD */
  30#define LCD_BPP                         LCD_COLOR8
  31#define CONFIG_LCD_LOGO
  32#undef LCD_TEST_PATTERN
  33#define CONFIG_LCD_INFO
  34#define CONFIG_LCD_INFO_BELOW_LOGO
  35#define CONFIG_ATMEL_LCD
  36#define CONFIG_ATMEL_LCD_RGB565
  37/* board specific(not enough SRAM) */
  38#define CONFIG_AT91SAM9G45_LCD_BASE             0x73E00000
  39
  40/*
  41 * BOOTP options
  42 */
  43#define CONFIG_BOOTP_BOOTFILESIZE
  44
  45/* SDRAM */
  46#define CONFIG_SYS_SDRAM_BASE           0x70000000
  47#define CONFIG_SYS_SDRAM_SIZE           0x08000000
  48
  49#define CONFIG_SYS_INIT_SP_ADDR \
  50        (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
  51
  52/* NAND flash */
  53#ifdef CONFIG_CMD_NAND
  54#define CONFIG_SYS_MAX_NAND_DEVICE              1
  55#define CONFIG_SYS_NAND_BASE                    ATMEL_BASE_CS3
  56#define CONFIG_SYS_NAND_DBW_8
  57/* our ALE is AD21 */
  58#define CONFIG_SYS_NAND_MASK_ALE                (1 << 21)
  59/* our CLE is AD22 */
  60#define CONFIG_SYS_NAND_MASK_CLE                (1 << 22)
  61#define CONFIG_SYS_NAND_ENABLE_PIN              AT91_PIN_PC14
  62#define CONFIG_SYS_NAND_READY_PIN               AT91_PIN_PC8
  63
  64#endif
  65
  66/* Ethernet */
  67#define CONFIG_RESET_PHY_R
  68#define CONFIG_AT91_WANTS_COMMON_PHY
  69
  70#define CONFIG_SYS_LOAD_ADDR            0x22000000      /* load address */
  71
  72#define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE
  73#define CONFIG_SYS_MEMTEST_END          0x23e00000
  74
  75#ifdef CONFIG_NAND_BOOT
  76/* bootstrap + u-boot + env in nandflash */
  77
  78#define CONFIG_BOOTCOMMAND                                              \
  79        "nand read 0x70000000 0x200000 0x300000;"                       \
  80        "bootm 0x70000000"
  81#elif CONFIG_SD_BOOT
  82/* bootstrap + u-boot + env + linux in mmc */
  83
  84#define CONFIG_BOOTCOMMAND      "fatload mmc 0:1 0x71000000 dtb; " \
  85                                "fatload mmc 0:1 0x72000000 zImage; " \
  86                                "bootz 0x72000000 - 0x71000000"
  87#endif
  88
  89/*
  90 * Size of malloc() pool
  91 */
  92#define CONFIG_SYS_MALLOC_LEN           ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
  93
  94/* Defines for SPL */
  95#define CONFIG_SPL_MAX_SIZE             0x010000
  96#define CONFIG_SPL_STACK                0x310000
  97
  98#define CONFIG_SYS_MONITOR_LEN          0x80000
  99
 100#ifdef CONFIG_SD_BOOT
 101
 102#define CONFIG_SPL_BSS_START_ADDR       0x70000000
 103#define CONFIG_SPL_BSS_MAX_SIZE         0x00080000
 104#define CONFIG_SYS_SPL_MALLOC_START     0x70080000
 105#define CONFIG_SYS_SPL_MALLOC_SIZE      0x00080000
 106
 107#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 108#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot.img"
 109
 110#elif CONFIG_NAND_BOOT
 111#define CONFIG_SPL_NAND_DRIVERS
 112#define CONFIG_SPL_NAND_BASE
 113#define CONFIG_SPL_NAND_ECC
 114#define CONFIG_SPL_NAND_SOFTECC
 115#define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
 116#define CONFIG_SYS_NAND_U_BOOT_SIZE     0x80000
 117#define CONFIG_SYS_NAND_5_ADDR_CYCLE
 118
 119#define CONFIG_SYS_NAND_PAGE_SIZE       0x800
 120#define CONFIG_SYS_NAND_BLOCK_SIZE      0x20000
 121#define CONFIG_SYS_NAND_PAGE_COUNT      64
 122#define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 123#define CONFIG_SYS_NAND_ECCSIZE         256
 124#define CONFIG_SYS_NAND_ECCBYTES        3
 125#define CONFIG_SYS_NAND_OOBSIZE         64
 126#define CONFIG_SYS_NAND_ECCPOS          { 40, 41, 42, 43, 44, 45, 46, 47, \
 127                                          48, 49, 50, 51, 52, 53, 54, 55, \
 128                                          56, 57, 58, 59, 60, 61, 62, 63, }
 129#endif
 130
 131#define CONFIG_SPL_ATMEL_SIZE
 132#define CONFIG_SYS_MASTER_CLOCK         132096000
 133#define CONFIG_SYS_AT91_PLLA            0x20c73f03
 134#define CONFIG_SYS_MCKR                 0x1301
 135#define CONFIG_SYS_MCKR_CSS             0x1302
 136
 137#endif
 138