LXR uboot/include/configs/corvus.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Common board functions for siemens AT91SAM9G45 based boards
   4 * (C) Copyright 2013 Siemens AG
   5 *
   6 * Based on:
   7 * U-Boot file: include/configs/at91sam9m10g45ek.h
   8 * (C) Copyright 2007-2008
   9 * Stelian Pop <stelian@popies.net>
  10 * Lead Tech Design <www.leadtechdesign.com>
  11 */
  12
  13#ifndef __CONFIG_H
  14#define __CONFIG_H
  15
  16#include <asm/hardware.h>
  17#include <linux/sizes.h>
  18
  19/*
  20 * Warning: changing CONFIG_SYS_TEXT_BASE requires
  21 * adapting the initial boot program.
  22 * Since the linker has to swallow that define, we must use a pure
  23 * hex number here!
  24 */
  25
  26#define CONFIG_ATMEL_LEGACY             /* required until (g)pio is fixed */
  27
  28/* ARM asynchronous clock */
  29#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
  30#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
  31
  32#define CONFIG_CMDLINE_TAG              /* enable passing of ATAGs      */
  33#define CONFIG_SETUP_MEMORY_TAGS
  34#define CONFIG_INITRD_TAG
  35#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
  36
  37/* general purpose I/O */
  38#define CONFIG_ATMEL_LEGACY             /* required until (g)pio is fixed */
  39#define CONFIG_AT91_GPIO
  40#define CONFIG_AT91_GPIO_PULLUP 1       /* keep pullups on peripheral pins */
  41
  42/* serial console */
  43#define CONFIG_USART_BASE               ATMEL_BASE_DBGU
  44#define CONFIG_USART_ID                 ATMEL_ID_SYS
  45
  46/* LED */
  47#define CONFIG_AT91_LED
  48#define CONFIG_RED_LED          AT91_PIN_PD31   /* this is the user1 led */
  49#define CONFIG_GREEN_LED        AT91_PIN_PD0    /* this is the user2 led */
  50
  51
  52/*
  53 * BOOTP options
  54 */
  55#define CONFIG_BOOTP_BOOTFILESIZE
  56
  57/* SDRAM */
  58#define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_CS6
  59#define CONFIG_SYS_SDRAM_SIZE           0x08000000
  60
  61#define CONFIG_SYS_INIT_SP_ADDR \
  62        (CONFIG_SYS_SDRAM_BASE + SZ_32K - GENERATED_GBL_DATA_SIZE)
  63
  64/* NAND flash */
  65#ifdef CONFIG_CMD_NAND
  66#define CONFIG_SYS_MAX_NAND_DEVICE              1
  67#define CONFIG_SYS_NAND_BASE                    ATMEL_BASE_CS3
  68#define CONFIG_SYS_NAND_DBW_8
  69/* our ALE is AD21 */
  70#define CONFIG_SYS_NAND_MASK_ALE                (1 << 21)
  71/* our CLE is AD22 */
  72#define CONFIG_SYS_NAND_MASK_CLE                (1 << 22)
  73#define CONFIG_SYS_NAND_ENABLE_PIN              AT91_PIN_PC14
  74#define CONFIG_SYS_NAND_READY_PIN               AT91_PIN_PC8
  75#define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
  76#endif
  77
  78/* Ethernet */
  79#define CONFIG_MACB
  80#define CONFIG_RMII
  81#define CONFIG_NET_RETRY_COUNT          20
  82#define CONFIG_AT91_WANTS_COMMON_PHY
  83
  84/* DFU class support */
  85#define CONFIG_SYS_DFU_DATA_BUF_SIZE    (SZ_1M)
  86#define DFU_MANIFEST_POLL_TIMEOUT       25000
  87
  88#define CONFIG_SYS_LOAD_ADDR    ATMEL_BASE_CS6
  89
  90/* bootstrap + u-boot + env in nandflash */
  91
  92#define CONFIG_BOOTCOMMAND                                              \
  93        "nand read 0x70000000 0x200000 0x300000;"                       \
  94        "bootm 0x70000000"
  95
  96/*
  97 * Size of malloc() pool
  98 */
  99#define CONFIG_SYS_MALLOC_LEN   ROUND(3 * CONFIG_ENV_SIZE + \
 100                                SZ_4M, 0x1000)
 101
 102/* Defines for SPL */
 103#define CONFIG_SPL_MAX_SIZE             (12 * SZ_1K)
 104#define CONFIG_SPL_STACK                (SZ_16K)
 105
 106#define CONFIG_SPL_BSS_START_ADDR       CONFIG_SPL_MAX_SIZE
 107#define CONFIG_SPL_BSS_MAX_SIZE         (SZ_2K)
 108
 109#define CONFIG_SPL_NAND_DRIVERS
 110#define CONFIG_SPL_NAND_BASE
 111#define CONFIG_SPL_NAND_ECC
 112#define CONFIG_SPL_NAND_RAW_ONLY
 113#define CONFIG_SPL_NAND_SOFTECC
 114#define CONFIG_SYS_NAND_U_BOOT_OFFS     0x20000
 115#define CONFIG_SYS_NAND_U_BOOT_SIZE     0x80000
 116#define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 117#define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
 118#define CONFIG_SYS_NAND_5_ADDR_CYCLE
 119
 120#define CONFIG_SYS_NAND_PAGE_SIZE       SZ_2K
 121#define CONFIG_SYS_NAND_BLOCK_SIZE      (SZ_128K)
 122#define CONFIG_SYS_NAND_PAGE_COUNT      (CONFIG_SYS_NAND_BLOCK_SIZE / \
 123                                         CONFIG_SYS_NAND_PAGE_SIZE)
 124#define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 125#define CONFIG_SYS_NAND_ECCSIZE         256
 126#define CONFIG_SYS_NAND_ECCBYTES        3
 127#define CONFIG_SYS_NAND_OOBSIZE         64
 128#define CONFIG_SYS_NAND_ECCPOS          { 40, 41, 42, 43, 44, 45, 46, 47, \
 129                                          48, 49, 50, 51, 52, 53, 54, 55, \
 130                                          56, 57, 58, 59, 60, 61, 62, 63, }
 131
 132#define CONFIG_SPL_ATMEL_SIZE
 133#define CONFIG_SYS_MASTER_CLOCK         132096000
 134#define AT91_PLL_LOCK_TIMEOUT           1000000
 135#define CONFIG_SYS_AT91_PLLA            0x20c73f03
 136#define CONFIG_SYS_MCKR                 0x1301
 137#define CONFIG_SYS_MCKR_CSS             0x1302
 138
 139#define CONFIG_SPL_PAD_TO               CONFIG_SYS_NAND_U_BOOT_OFFS
 140#define CONFIG_SYS_SPL_LEN              CONFIG_SPL_PAD_TO
 141
 142#endif
 143