LXR uboot/include/configs/cyrus.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Based on corenet_ds.h
   4 */
   5
   6#ifndef __CONFIG_H
   7#define __CONFIG_H
   8
   9#if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040)
  10#error Must call Cyrus CONFIG with a specific CPU enabled.
  11#endif
  12
  13#define CONFIG_SDCARD
  14#define CONFIG_FSL_SATA_V2
  15#define CONFIG_PCIE3
  16#define CONFIG_PCIE4
  17#ifdef CONFIG_ARCH_P5020
  18#define CONFIG_SYS_FSL_RAID_ENGINE
  19#define CONFIG_SYS_DPAA_RMAN
  20#endif
  21#define CONFIG_SYS_DPAA_PME
  22
  23/*
  24 * Corenet DS style board configuration file
  25 */
  26#define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  27#define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  28#define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg
  29#if defined(CONFIG_ARCH_P5020)
  30#define CONFIG_SYS_CLK_FREQ 133000000
  31#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg
  32#elif defined(CONFIG_ARCH_P5040)
  33#define CONFIG_SYS_CLK_FREQ 100000000
  34#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg
  35#endif
  36
  37/* High Level Configuration Options */
  38#define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  39
  40#define CONFIG_SYS_MMC_MAX_DEVICE     1
  41
  42#define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  43#define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  44#define CONFIG_PCIE1                    /* PCIE controller 1 */
  45#define CONFIG_PCIE2                    /* PCIE controller 2 */
  46#define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  47#define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  48
  49#define CONFIG_ENV_OVERWRITE
  50
  51#if defined(CONFIG_SDCARD)
  52#define CONFIG_FSL_FIXED_MMC_LOCATION
  53#define CONFIG_SYS_MMC_ENV_DEV          0
  54#endif
  55
  56/*
  57 * These can be toggled for performance analysis, otherwise use default.
  58 */
  59#define CONFIG_SYS_CACHE_STASHING
  60#define CONFIG_BACKSIDE_L2_CACHE
  61#define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  62#define CONFIG_BTB                      /* toggle branch predition */
  63#define CONFIG_DDR_ECC
  64#ifdef CONFIG_DDR_ECC
  65#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  66#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  67#endif
  68
  69#define CONFIG_ENABLE_36BIT_PHYS
  70
  71#ifdef CONFIG_PHYS_64BIT
  72#define CONFIG_ADDR_MAP
  73#define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
  74#endif
  75
  76/* test POST memory test */
  77#undef CONFIG_POST
  78#define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  79#define CONFIG_SYS_MEMTEST_END          0x00400000
  80
  81/*
  82 *  Config the L3 Cache as L3 SRAM
  83 */
  84#define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
  85#ifdef CONFIG_PHYS_64BIT
  86#define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
  87#else
  88#define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
  89#endif
  90#define CONFIG_SYS_L3_SIZE              (1024 << 10)
  91#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  92
  93#ifdef CONFIG_PHYS_64BIT
  94#define CONFIG_SYS_DCSRBAR              0xf0000000
  95#define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  96#endif
  97
  98/*
  99 * DDR Setup
 100 */
 101#define CONFIG_VERY_BIG_RAM
 102#define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 103#define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 104
 105#define CONFIG_DIMM_SLOTS_PER_CTLR      1
 106#define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 107
 108#define CONFIG_DDR_SPD
 109
 110#define CONFIG_SYS_SPD_BUS_NUM  1
 111#define SPD_EEPROM_ADDRESS1     0x51
 112#define SPD_EEPROM_ADDRESS2     0x52
 113#define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 114
 115/*
 116 * Local Bus Definitions
 117 */
 118
 119#define CONFIG_SYS_LBC0_BASE            0xe0000000 /* Start of LBC Registers */
 120#ifdef CONFIG_PHYS_64BIT
 121#define CONFIG_SYS_LBC0_BASE_PHYS       0xfe0000000ull
 122#else
 123#define CONFIG_SYS_LBC0_BASE_PHYS       CONFIG_SYS_LBC0_BASE
 124#endif
 125
 126#define CONFIG_SYS_LBC1_BASE            0xe1000000 /* Start of LBC Registers */
 127#ifdef CONFIG_PHYS_64BIT
 128#define CONFIG_SYS_LBC1_BASE_PHYS       0xfe1000000ull
 129#else
 130#define CONFIG_SYS_LBC1_BASE_PHYS       CONFIG_SYS_LBC1_BASE
 131#endif
 132
 133/* Set the local bus clock 1/16 of platform clock */
 134#define CONFIG_SYS_LBC_LCRR             (LCRR_CLKDIV_16 | LCRR_EADC_1)
 135
 136#define CONFIG_SYS_BR0_PRELIM \
 137(BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V)
 138#define CONFIG_SYS_BR1_PRELIM \
 139(BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V)
 140
 141#define CONFIG_SYS_OR0_PRELIM   0xfff00010
 142#define CONFIG_SYS_OR1_PRELIM   0xfff00010
 143
 144#define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 145
 146#if defined(CONFIG_RAMBOOT_PBL)
 147#define CONFIG_SYS_RAMBOOT
 148#endif
 149
 150#define CONFIG_HWCONFIG
 151
 152/* define to use L1 as initial stack */
 153#define CONFIG_L1_INIT_RAM
 154#define CONFIG_SYS_INIT_RAM_LOCK
 155#define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 156#ifdef CONFIG_PHYS_64BIT
 157#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 158#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 159/* The assembler doesn't like typecast */
 160#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 161        ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 162          CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 163#else
 164#define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
 165#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 166#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 167#endif
 168#define CONFIG_SYS_INIT_RAM_SIZE                0x00004000      /* Size of used area in RAM */
 169
 170#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 171#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 172
 173#define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 174#define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 175
 176/* Serial Port - controlled on board with jumper J8
 177 * open - index 2
 178 * shorted - index 1
 179 */
 180#define CONFIG_SYS_NS16550_SERIAL
 181#define CONFIG_SYS_NS16550_REG_SIZE     1
 182#define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 183
 184#define CONFIG_SYS_BAUDRATE_TABLE       \
 185{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 186
 187#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 188#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 189#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 190#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 191
 192/* I2C */
 193#define CONFIG_SYS_I2C
 194#define CONFIG_SYS_I2C_FSL
 195#define CONFIG_I2C_MULTI_BUS
 196#define CONFIG_I2C_CMD_TREE
 197#define CONFIG_SYS_FSL_I2C_SPEED                400000  /* I2C speed and slave address */
 198#define CONFIG_SYS_FSL_I2C_SLAVE                0x7F
 199#define CONFIG_SYS_FSL_I2C_OFFSET               0x118000
 200#define CONFIG_SYS_FSL_I2C2_SPEED               400000  /* I2C speed and slave address */
 201#define CONFIG_SYS_FSL_I2C2_SLAVE               0x7F
 202#define CONFIG_SYS_FSL_I2C2_OFFSET              0x118100
 203#define CONFIG_SYS_FSL_I2C3_SPEED               400000  /* I2C speed and slave address */
 204#define CONFIG_SYS_FSL_I2C3_SLAVE               0x7F
 205#define CONFIG_SYS_FSL_I2C3_OFFSET              0x119000
 206#define CONFIG_SYS_FSL_I2C4_SPEED               400000  /* I2C speed and slave address */
 207#define CONFIG_SYS_FSL_I2C4_SLAVE               0x7F
 208#define CONFIG_SYS_FSL_I2C4_OFFSET              0x119100
 209
 210#define CONFIG_ID_EEPROM
 211#define CONFIG_SYS_I2C_EEPROM_NXID
 212#define CONFIG_SYS_EEPROM_BUS_NUM       0
 213#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 214#define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 215
 216#define CONFIG_SYS_I2C_GENERIC_MAC
 217#define CONFIG_SYS_I2C_MAC1_BUS 3
 218#define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57
 219#define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2
 220#define CONFIG_SYS_I2C_MAC2_BUS 0
 221#define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50
 222#define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa
 223
 224#define CONFIG_RTC_MCP79411             1
 225#define CONFIG_SYS_RTC_BUS_NUM          3
 226#define CONFIG_SYS_I2C_RTC_ADDR         0x6f
 227
 228/*
 229 * eSPI - Enhanced SPI
 230 */
 231
 232/*
 233 * General PCI
 234 * Memory space is mapped 1-1, but I/O space must start from 0.
 235 */
 236
 237/* controller 1, direct to uli, tgtid 3, Base address 20000 */
 238#define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 239#ifdef CONFIG_PHYS_64BIT
 240#define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 241#define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 242#else
 243#define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 244#define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 245#endif
 246#define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 247#define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 248#define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 249#ifdef CONFIG_PHYS_64BIT
 250#define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 251#else
 252#define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 253#endif
 254#define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 255
 256/* controller 2, Slot 2, tgtid 2, Base address 201000 */
 257#define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 258#ifdef CONFIG_PHYS_64BIT
 259#define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 260#define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 261#else
 262#define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 263#define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 264#endif
 265#define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 266#define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 267#define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 268#ifdef CONFIG_PHYS_64BIT
 269#define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 270#else
 271#define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 272#endif
 273#define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 274
 275/* controller 3, Slot 1, tgtid 1, Base address 202000 */
 276#define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 277#ifdef CONFIG_PHYS_64BIT
 278#define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 279#define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 280#else
 281#define CONFIG_SYS_PCIE3_MEM_BUS        0xc0000000
 282#define CONFIG_SYS_PCIE3_MEM_PHYS       0xc0000000
 283#endif
 284#define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 285#define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 286#define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 287#ifdef CONFIG_PHYS_64BIT
 288#define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 289#else
 290#define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 291#endif
 292#define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 293
 294/* controller 4, Base address 203000 */
 295#define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 296#define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 297#define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
 298#define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 299#define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 300#define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 301
 302/* Qman/Bman */
 303#define CONFIG_SYS_BMAN_NUM_PORTALS     10
 304#define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 305#ifdef CONFIG_PHYS_64BIT
 306#define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 307#else
 308#define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 309#endif
 310#define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 311#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 312#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 313#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 314#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 315#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 316                                         CONFIG_SYS_BMAN_CENA_SIZE)
 317#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 318#define CONFIG_SYS_BMAN_SWP_ISDR_REG   0xE08
 319#define CONFIG_SYS_QMAN_NUM_PORTALS     10
 320#define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 321#ifdef CONFIG_PHYS_64BIT
 322#define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 323#else
 324#define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 325#endif
 326#define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 327#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 328#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 329#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 330#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 331#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 332                                          CONFIG_SYS_QMAN_CENA_SIZE)
 333#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 334#define CONFIG_SYS_QMAN_SWP_ISDR_REG   0xE08
 335
 336#define CONFIG_SYS_DPAA_FMAN
 337/* Default address of microcode for the Linux Fman driver */
 338/*
 339 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 340 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 341 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 342 */
 343#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
 344
 345#define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 346#define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 347
 348#ifdef CONFIG_PCI
 349#define CONFIG_PCI_INDIRECT_BRIDGE
 350
 351#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 352#endif  /* CONFIG_PCI */
 353
 354/* SATA */
 355#ifdef CONFIG_FSL_SATA_V2
 356#define CONFIG_SYS_SATA_MAX_DEVICE      2
 357#define CONFIG_SATA1
 358#define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 359#define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 360#define CONFIG_SATA2
 361#define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 362#define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 363
 364#define CONFIG_LBA48
 365#endif
 366
 367#ifdef CONFIG_FMAN_ENET
 368#define CONFIG_SYS_TBIPA_VALUE  8
 369#define CONFIG_ETHPRIME         "FM1@DTSEC4"
 370#endif
 371
 372/*
 373 * Environment
 374 */
 375#define CONFIG_LOADS_ECHO               /* echo on for serial download */
 376#define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 377
 378/*
 379 * USB
 380 */
 381#define CONFIG_HAS_FSL_DR_USB
 382#define CONFIG_HAS_FSL_MPH_USB
 383
 384#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 385#define CONFIG_USB_EHCI_FSL
 386#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 387#define CONFIG_EHCI_IS_TDI
 388 /* _VIA_CONTROL_EP  */
 389#endif
 390
 391#ifdef CONFIG_MMC
 392#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 393#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 394#endif
 395
 396/*
 397 * Miscellaneous configurable options
 398 */
 399#define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 400
 401/*
 402 * For booting Linux, the board info and command line data
 403 * have to be in the first 64 MB of memory, since this is
 404 * the maximum mapped by the Linux kernel during initialization.
 405 */
 406#define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 407#define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 408
 409#ifdef CONFIG_CMD_KGDB
 410#define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 411#endif
 412
 413/*
 414 * Environment Configuration
 415 */
 416#define CONFIG_ROOTPATH         "/opt/nfsroot"
 417#define CONFIG_BOOTFILE         "uImage"
 418#define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 419
 420/* default location for tftp and bootm */
 421#define CONFIG_LOADADDR         1000000
 422
 423#define __USB_PHY_TYPE  utmi
 424
 425#define CONFIG_EXTRA_ENV_SETTINGS \
 426"hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 427"bank_intlv=cs0_cs1;"                                   \
 428"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 429"usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 430"netdev=eth0\0"                                         \
 431"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 432"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"                     \
 433"consoledev=ttyS0\0"                                    \
 434"ramdiskaddr=2000000\0"                                 \
 435"fdtaddr=1e00000\0"                                     \
 436"bdev=sda3\0"
 437
 438#define CONFIG_HDBOOT                                   \
 439"setenv bootargs root=/dev/$bdev rw "           \
 440"console=$consoledev,$baudrate $othbootargs;"   \
 441"tftp $loadaddr $bootfile;"                     \
 442"tftp $fdtaddr $fdtfile;"                       \
 443"bootm $loadaddr - $fdtaddr"
 444
 445#define CONFIG_NFSBOOTCOMMAND                   \
 446"setenv bootargs root=/dev/nfs rw "     \
 447"nfsroot=$serverip:$rootpath "          \
 448"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 449"console=$consoledev,$baudrate $othbootargs;"   \
 450"tftp $loadaddr $bootfile;"             \
 451"tftp $fdtaddr $fdtfile;"               \
 452"bootm $loadaddr - $fdtaddr"
 453
 454#define CONFIG_RAMBOOTCOMMAND                           \
 455"setenv bootargs root=/dev/ram rw "             \
 456"console=$consoledev,$baudrate $othbootargs;"   \
 457"tftp $ramdiskaddr $ramdiskfile;"               \
 458"tftp $loadaddr $bootfile;"                     \
 459"tftp $fdtaddr $fdtfile;"                       \
 460"bootm $loadaddr $ramdiskaddr $fdtaddr"
 461
 462#define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 463
 464#include <asm/fsl_secure_boot.h>
 465
 466#endif  /* __CONFIG_H */
 467