LXR uboot/include/configs/devkit8000.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * (C) Copyright 2006-2008
   4 * Texas Instruments.
   5 * Richard Woodruff <r-woodruff2@ti.com>
   6 * Syed Mohammed Khasim <x0khasim@ti.com>
   7 *
   8 * (C) Copyright 2009
   9 * Frederik Kriewitz <frederik@kriewitz.eu>
  10 *
  11 * Configuration settings for the DevKit8000 board.
  12 */
  13
  14#ifndef __CONFIG_H
  15#define __CONFIG_H
  16
  17/* High Level Configuration Options */
  18#define CONFIG_MACH_TYPE        MACH_TYPE_DEVKIT8000
  19
  20/*
  21 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
  22 * 64 bytes before this address should be set aside for u-boot.img's
  23 * header. That is 0x800FFFC0--0x80100000 should not be used for any
  24 * other needs.
  25 */
  26
  27#define CONFIG_SPL_BSS_START_ADDR       0x80000500 /* leave space for bootargs*/
  28#define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  29
  30#define CONFIG_SYS_SPL_MALLOC_START     0x80208000
  31#define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000        /* 1 MB */
  32
  33/*  Physical Memory Map  */
  34
  35#include <configs/ti_omap3_common.h>
  36
  37#define CONFIG_REVISION_TAG             1
  38
  39/* Size of malloc() pool */
  40#undef CONFIG_SYS_MALLOC_LEN
  41#define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (128 << 10))
  42
  43/* Hardware drivers */
  44/* DM9000 */
  45#define CONFIG_NET_RETRY_COUNT          20
  46#define CONFIG_DRIVER_DM9000            1
  47#define CONFIG_DM9000_BASE              0x2c000000
  48#define DM9000_IO                       CONFIG_DM9000_BASE
  49#define DM9000_DATA                     (CONFIG_DM9000_BASE + 0x400)
  50#define CONFIG_DM9000_USE_16BIT         1
  51#define CONFIG_DM9000_NO_SROM           1
  52#undef  CONFIG_DM9000_DEBUG
  53
  54/* TWL4030 */
  55
  56/* Board NAND Info */
  57#define CONFIG_JFFS2_NAND
  58/* nand device jffs2 lives on */
  59#define CONFIG_JFFS2_DEV                "nand0"
  60/* start of jffs2 partition */
  61#define CONFIG_JFFS2_PART_OFFSET        0x680000
  62#define CONFIG_JFFS2_PART_SIZE          0xf980000       /* size of jffs2 */
  63                                                        /* partition */
  64
  65/* BOOTP/DHCP options */
  66#define CONFIG_BOOTP_NISDOMAIN
  67#define CONFIG_BOOTP_BOOTFILESIZE
  68#define CONFIG_BOOTP_DNS2
  69#define CONFIG_BOOTP_SEND_HOSTNAME
  70#define CONFIG_BOOTP_TIMEOFFSET
  71#undef CONFIG_BOOTP_VENDOREX
  72
  73/* Environment information */
  74#define CONFIG_EXTRA_ENV_SETTINGS \
  75        "loadaddr=0x82000000\0" \
  76        "console=ttyO2,115200n8\0" \
  77        "mmcdev=0\0" \
  78        "vram=12M\0" \
  79        "dvimode=1024x768MR-16@60\0" \
  80        "defaultdisplay=dvi\0" \
  81        "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
  82        "kernelopts=rw\0" \
  83        "commonargs=" \
  84                "setenv bootargs console=${console} " \
  85                "vram=${vram} " \
  86                "omapfb.mode=dvi:${dvimode} " \
  87                "omapdss.def_disp=${defaultdisplay}\0" \
  88        "mmcargs=" \
  89                "run commonargs; " \
  90                "setenv bootargs ${bootargs} " \
  91                "root=/dev/mmcblk0p2 " \
  92                "rootwait " \
  93                "${kernelopts}\0" \
  94        "nandargs=" \
  95                "run commonargs; " \
  96                "setenv bootargs ${bootargs} " \
  97                "omapfb.mode=dvi:${dvimode} " \
  98                "omapdss.def_disp=${defaultdisplay} " \
  99                "root=/dev/mtdblock4 " \
 100                "rootfstype=jffs2 " \
 101                "${kernelopts}\0" \
 102        "netargs=" \
 103                "run commonargs; " \
 104                "setenv bootargs ${bootargs} " \
 105                "root=/dev/nfs " \
 106                "nfsroot=${serverip}:${rootpath},${nfsopts} " \
 107                "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
 108                "${kernelopts} " \
 109                "dnsip1=${dnsip} " \
 110                "dnsip2=${dnsip2}\0" \
 111        "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 112        "bootscript=echo Running bootscript from mmc ...; " \
 113                "source ${loadaddr}\0" \
 114        "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 115        "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
 116        "mmcboot=echo Booting from mmc ...; " \
 117                "run mmcargs; " \
 118                "bootm ${loadaddr}\0" \
 119        "nandboot=echo Booting from nand ...; " \
 120                "run nandargs; " \
 121                "nand read ${loadaddr} 280000 400000; " \
 122                "bootm ${loadaddr}\0" \
 123        "netboot=echo Booting from network ...; " \
 124                "dhcp ${loadaddr}; " \
 125                "run netargs; " \
 126                "bootm ${loadaddr}\0" \
 127        "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
 128                        "if run loadbootscript; then " \
 129                                "run bootscript; " \
 130                        "else " \
 131                                "if run loaduimage; then " \
 132                                        "run mmcboot; " \
 133                                "else run nandboot; " \
 134                                "fi; " \
 135                        "fi; " \
 136                "else run nandboot; fi\0"
 137
 138#define CONFIG_BOOTCOMMAND "run autoboot"
 139
 140/* Boot Argument Buffer Size */
 141#define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0 + 0x07000000)
 142#define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + \
 143                                        0x01000000) /* 16MB */
 144
 145/* SRAM config */
 146#define CONFIG_SYS_SRAM_START              0x40200000
 147#define CONFIG_SYS_SRAM_SIZE               0x10000
 148
 149/* Defines for SPL */
 150
 151/* NAND boot config */
 152#define CONFIG_SYS_NAND_5_ADDR_CYCLE
 153#define CONFIG_SYS_NAND_PAGE_COUNT      64
 154#define CONFIG_SYS_NAND_PAGE_SIZE       2048
 155#define CONFIG_SYS_NAND_OOBSIZE         64
 156#define CONFIG_SYS_NAND_BLOCK_SIZE      (128*1024)
 157#define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 158#define CONFIG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9,\
 159                                                10, 11, 12, 13}
 160
 161#define CONFIG_SYS_NAND_ECCSIZE         512
 162#define CONFIG_SYS_NAND_ECCBYTES        3
 163#define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_HW
 164
 165#define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 166#define CONFIG_SYS_NAND_U_BOOT_SIZE     0x200000
 167
 168/* SPL OS boot options */
 169#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
 170
 171#undef CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
 172#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR
 173#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
 174#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */
 175#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR   0x8   /* address 0x1000 */
 176#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS  8     /* 4KB */
 177
 178#undef CONFIG_SYS_SPL_ARGS_ADDR
 179#define CONFIG_SYS_SPL_ARGS_ADDR        (PHYS_SDRAM_1 + 0x100)
 180
 181#endif /* __CONFIG_H */
 182