1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123) 4 * 5 * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de> 6 */ 7 8#ifndef _CONFIG_EB_CPU5282_H_ 9#define _CONFIG_EB_CPU5282_H_ 10 11#undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP 12 13/*----------------------------------------------------------------------* 14 * High Level Configuration Options (easy to change) * 15 *----------------------------------------------------------------------*/ 16 17#define CONFIG_MCFUART 18#define CONFIG_SYS_UART_PORT (0) 19 20#undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */ 21 22#define CONFIG_BOOTCOMMAND "printenv" 23 24/*----------------------------------------------------------------------* 25 * Options * 26 *----------------------------------------------------------------------*/ 27 28#define CONFIG_BOOT_RETRY_TIME -1 29#define CONFIG_RESET_TO_RETRY 30#define CONFIG_SPLASH_SCREEN 31 32#define CONFIG_HW_WATCHDOG 33 34#define STATUS_LED_ACTIVE 0 35 36/*----------------------------------------------------------------------* 37 * Configuration for environment * 38 * Environment is in the second sector of the first 256k of flash * 39 *----------------------------------------------------------------------*/ 40 41/* 42 * BOOTP options 43 */ 44#define CONFIG_BOOTP_BOOTFILESIZE 45 46/* 47 * Command line configuration. 48 */ 49 50#define CONFIG_MCFTMR 51 52#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 53#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 54 55#define CONFIG_SYS_LOAD_ADDR 0x20000 56 57#define CONFIG_SYS_MEMTEST_START 0x100000 58#define CONFIG_SYS_MEMTEST_END 0x400000 59/*#define CONFIG_SYS_DRAM_TEST 1 */ 60#undef CONFIG_SYS_DRAM_TEST 61 62/*----------------------------------------------------------------------* 63 * Clock and PLL Configuration * 64 *----------------------------------------------------------------------*/ 65#define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */ 66 67/* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */ 68 69#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ 70#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ 71 72/*----------------------------------------------------------------------* 73 * Network * 74 *----------------------------------------------------------------------*/ 75 76#define CONFIG_MCFFEC 77#define CONFIG_MII_INIT 1 78#define CONFIG_SYS_DISCOVER_PHY 79#define CONFIG_SYS_RX_ETH_BUFFER 8 80#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 81 82#define CONFIG_SYS_FEC0_PINMUX 0 83#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 84#define MCFFEC_TOUT_LOOP 50000 85 86#define CONFIG_OVERWRITE_ETHADDR_ONCE 87 88/*------------------------------------------------------------------------- 89 * Low Level Configuration Settings 90 * (address mappings, register initial values, etc.) 91 * You should know what you are doing if you make changes here. 92 *-----------------------------------------------------------------------*/ 93 94#define CONFIG_SYS_MBAR 0x40000000 95 96/*----------------------------------------------------------------------- 97 * Definitions for initial stack pointer and data area (in DPRAM) 98 *-----------------------------------------------------------------------*/ 99 100#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 101#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 102#define CONFIG_SYS_GBL_DATA_OFFSET \ 103 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 104#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 105 106/*----------------------------------------------------------------------- 107 * Start addresses for the final memory configuration 108 * (Set up by the startup code) 109 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 110 */ 111#define CONFIG_SYS_SDRAM_BASE0 0x00000000 112#define CONFIG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */ 113 114#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0 115#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0 116 117#define CONFIG_SYS_MONITOR_LEN 0x20000 118#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 119#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 120 121/* 122 * For booting Linux, the board info and command line data 123 * have to be in the first 8 MB of memory, since this is 124 * the maximum mapped by the Linux kernel during initialization ?? 125 */ 126#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 127 128/*----------------------------------------------------------------------- 129 * FLASH organization 130 */ 131#define CONFIG_FLASH_SHOW_PROGRESS 45 132 133#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 134#define CONFIG_SYS_INT_FLASH_BASE 0xF0000000 135#define CONFIG_SYS_INT_FLASH_ENABLE 0x21 136 137#define CONFIG_SYS_MAX_FLASH_SECT 128 138#define CONFIG_SYS_MAX_FLASH_BANKS 1 139#define CONFIG_SYS_FLASH_ERASE_TOUT 10000000 140 141#define CONFIG_SYS_FLASH_SIZE 16*1024*1024 142#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 143 144#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 145 146/*----------------------------------------------------------------------- 147 * Cache Configuration 148 */ 149#define CONFIG_SYS_CACHELINE_SIZE 16 150 151#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 152 CONFIG_SYS_INIT_RAM_SIZE - 8) 153#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 154 CONFIG_SYS_INIT_RAM_SIZE - 4) 155#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) 156#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 157 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 158 CF_ACR_EN | CF_ACR_SM_ALL) 159#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ 160 CF_CACR_CEIB | CF_CACR_DBWE | \ 161 CF_CACR_EUSP) 162 163/*----------------------------------------------------------------------- 164 * Memory bank definitions 165 */ 166 167#define CONFIG_SYS_CS0_BASE 0xFF000000 168#define CONFIG_SYS_CS0_CTRL 0x00001980 169#define CONFIG_SYS_CS0_MASK 0x00FF0001 170 171#define CONFIG_SYS_CS2_BASE 0xE0000000 172#define CONFIG_SYS_CS2_CTRL 0x00001980 173#define CONFIG_SYS_CS2_MASK 0x000F0001 174 175#define CONFIG_SYS_CS3_BASE 0xE0100000 176#define CONFIG_SYS_CS3_CTRL 0x00001980 177#define CONFIG_SYS_CS3_MASK 0x000F0001 178 179/*----------------------------------------------------------------------- 180 * Port configuration 181 */ 182#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ 183#define CONFIG_SYS_PADDR 0x0000000 184#define CONFIG_SYS_PADAT 0x0000000 185 186#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ 187#define CONFIG_SYS_PBDDR 0x0000000 188#define CONFIG_SYS_PBDAT 0x0000000 189 190#define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ 191#define CONFIG_SYS_PCDDR 0x0000000 192#define CONFIG_SYS_PCDAT 0x0000000 193 194#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ 195#define CONFIG_SYS_PCDDR 0x0000000 196#define CONFIG_SYS_PCDAT 0x0000000 197 198#define CONFIG_SYS_PASPAR 0x0F0F 199#define CONFIG_SYS_PEHLPAR 0xC0 200#define CONFIG_SYS_PUAPAR 0x0F 201#define CONFIG_SYS_DDRUA 0x05 202#define CONFIG_SYS_PJPAR 0xFF 203 204/*----------------------------------------------------------------------- 205 * I2C 206 */ 207 208#define CONFIG_SYS_I2C 209#define CONFIG_SYS_I2C_FSL 210 211#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 212#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 213 214#define CONFIG_SYS_FSL_I2C_SPEED 100000 215#define CONFIG_SYS_FSL_I2C_SLAVE 0 216 217#ifdef CONFIG_CMD_DATE 218#define CONFIG_RTC_DS1338 219#define CONFIG_I2C_RTC_ADDR 0x68 220#endif 221 222/*----------------------------------------------------------------------- 223 * VIDEO configuration 224 */ 225 226#ifdef CONFIG_VIDEO 227#define CONFIG_VIDEO_VCXK 1 228 229#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2 230#define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1 231#define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS2_BASE 232 233#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT 234#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR 235#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN 0x0001 236 237#define CONFIG_SYS_VCXK_ENABLE_PORT MCFGPTB_GPTPORT 238#define CONFIG_SYS_VCXK_ENABLE_DDR MCFGPTB_GPTDDR 239#define CONFIG_SYS_VCXK_ENABLE_PIN 0x0002 240 241#define CONFIG_SYS_VCXK_REQUEST_PORT MCFGPTB_GPTPORT 242#define CONFIG_SYS_VCXK_REQUEST_DDR MCFGPTB_GPTDDR 243#define CONFIG_SYS_VCXK_REQUEST_PIN 0x0004 244 245#define CONFIG_SYS_VCXK_INVERT_PORT MCFGPIO_PORTE 246#define CONFIG_SYS_VCXK_INVERT_DDR MCFGPIO_DDRE 247#define CONFIG_SYS_VCXK_INVERT_PIN MCFGPIO_PORT2 248 249#endif /* CONFIG_VIDEO */ 250#endif /* _CONFIG_M5282EVB_H */ 251/*---------------------------------------------------------------------*/ 252