1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2012 Atmel Corporation 4 * Copyright (C) 2019 Stefan Roese <sr@denx.de> 5 * 6 * Configuation settings for the GARDENA smart Gateway (AT91SAM9G25) 7 */ 8 9#ifndef __CONFIG_H__ 10#define __CONFIG_H__ 11 12/* ARM asynchronous clock */ 13#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 14#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ 15 16#ifndef CONFIG_SPL_BUILD 17#define CONFIG_SKIP_LOWLEVEL_INIT 18#endif 19#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY 20 21/* general purpose I/O */ 22#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ 23 24/* SDRAM */ 25#define CONFIG_SYS_SDRAM_BASE 0x20000000 26#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ 27 28#define CONFIG_SYS_INIT_SP_ADDR \ 29 (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) 30 31#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) 32 33/* NAND flash */ 34#define CONFIG_SYS_MAX_NAND_DEVICE 1 35#define CONFIG_SYS_NAND_BASE 0x40000000 36#define CONFIG_SYS_NAND_DBW_8 1 37/* our ALE is AD21 */ 38#define CONFIG_SYS_NAND_MASK_ALE BIT(21) 39/* our CLE is AD22 */ 40#define CONFIG_SYS_NAND_MASK_CLE BIT(22) 41#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 42#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 43 44#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 45 46/* SPL */ 47#define CONFIG_SPL_MAX_SIZE 0x7000 48#define CONFIG_SPL_STACK 0x308000 49 50#define CONFIG_SPL_BSS_START_ADDR 0x20000000 51#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 52#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 53#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 54 55#define CONFIG_SYS_MONITOR_LEN (512 << 10) 56 57#define CONFIG_SYS_MASTER_CLOCK 132096000 58#define CONFIG_SYS_AT91_PLLA 0x20c73f03 59#define CONFIG_SYS_MCKR 0x1301 60#define CONFIG_SYS_MCKR_CSS 0x1302 61 62#define CONFIG_SPL_NAND_DRIVERS 63#define CONFIG_SPL_NAND_BASE 64#define CONFIG_SPL_NAND_RAW_ONLY 65#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 66#define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000 67#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE 68#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 69#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 70 71#define CONFIG_SYS_NAND_5_ADDR_CYCLE 72#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 73#define CONFIG_SYS_NAND_PAGE_COUNT 64 74#define CONFIG_SYS_NAND_OOBSIZE 64 75#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 76#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 77 78#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS 79#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO 80 81#endif 82