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11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14
15
16
17#define CONFIG_FSL_ELBC
18
19#define CONFIG_BOOT_RETRY_TIME 900
20#define CONFIG_BOOT_RETRY_MIN 30
21#define CONFIG_RESET_TO_RETRY
22
23#define CONFIG_SYS_SICRH 0x00000000
24#define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D)
25
26#define CONFIG_HWCONFIG
27
28
29
30
31#define CONFIG_SYS_INIT_RAM_LOCK
32#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
33#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
34#define CONFIG_SYS_GBL_DATA_SIZE 0x100
35#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
36 - CONFIG_SYS_GBL_DATA_SIZE)
37#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
38
39
40
41
42
43
44
45#define CONFIG_SYS_SDRAM_BASE 0x00000000
46
47
48
49
50
51#define CONFIG_SYS_DDR_SIZE 256
52#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\
53 0x00010000 |\
54 CSCONFIG_ROW_BIT_13 |\
55 CSCONFIG_COL_BIT_10)
56
57#define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG | \
58 CSCONFIG_BANK_BIT_3)
59
60#define CONFIG_SYS_DDR_TIMING_3 (1 << 16)
61#define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\
62 (3 << TIMING_CFG0_WRT_SHIFT) |\
63 (3 << TIMING_CFG0_RRT_SHIFT) |\
64 (3 << TIMING_CFG0_WWT_SHIFT) |\
65 (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
66 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
67 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
68 (2 << TIMING_CFG0_MRS_CYC_SHIFT))
69#define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
70 (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
71 (4 << TIMING_CFG1_ACTTORW_SHIFT) |\
72 (7 << TIMING_CFG1_CASLAT_SHIFT) |\
73 (4 << TIMING_CFG1_REFREC_SHIFT) |\
74 (4 << TIMING_CFG1_WRREC_SHIFT) |\
75 (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
76 (2 << TIMING_CFG1_WRTORD_SHIFT))
77#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
78 (5 << TIMING_CFG2_CPO_SHIFT) |\
79 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
80 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
81 (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
82 (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
83 (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
84
85#define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
86 (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
87
88#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN |\
89 SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
90 SDRAM_CFG_DBW_32 |\
91 SDRAM_CFG_SDRAM_TYPE_DDR2)
92
93#define CONFIG_SYS_SDRAM_CFG2 0x00401000
94#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
95 (0x0242 << SDRAM_MODE_SD_SHIFT))
96#define CONFIG_SYS_DDR_MODE_2 0x00000000
97#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
98#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\
99 DDRCDR_PZ_NOMZ |\
100 DDRCDR_NZ_NOMZ |\
101 DDRCDR_ODT |\
102 DDRCDR_M_ODR |\
103 DDRCDR_Q_DRN)
104
105
106
107
108#define CONFIG_TSEC1
109#define CONFIG_TSEC2
110
111
112
113
114#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
115#define CONFIG_FLASH_SHOW_PROGRESS 50
116
117#define CONFIG_SYS_FLASH_BASE 0xFF800000
118#define CONFIG_SYS_FLASH_SIZE 8
119
120
121#define CONFIG_SYS_MAX_FLASH_BANKS 1
122#define CONFIG_SYS_MAX_FLASH_SECT 128
123
124#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
125#define CONFIG_SYS_FLASH_WRITE_TOUT 500
126
127
128
129
130#define CONFIG_SYS_NAND_BASE 0xE1000000
131#define CONFIG_SYS_MAX_NAND_DEVICE 1
132#define CONFIG_SYS_NAND_MAX_CHIPS 1
133#define CONFIG_NAND_FSL_ELBC
134#define CONFIG_SYS_NAND_PAGE_SIZE (2048)
135#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
136#define NAND_CACHE_PAGES 64
137
138
139
140
141
142#define CONFIG_SYS_MRAM_BASE 0xE2000000
143#define CONFIG_SYS_MRAM_SIZE 0x20000
144
145#define CONFIG_SYS_OR_TIMING_MRAM
146
147
148
149
150
151#define CONFIG_SYS_CPLD_BASE 0xE3000000
152#define CONFIG_SYS_CPLD_SIZE 0x8000
153
154#define CONFIG_SYS_OR_TIMING_MRAM
155
156
157
158
159
160#define CONFIG_WATCHDOG 1
161#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
162
163
164
165
166#define CONFIG_SYS_I2C
167#define CONFIG_SYS_I2C_FSL
168#define CONFIG_SYS_FSL_I2C_SPEED 400000
169#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
170#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
171#define CONFIG_RTC_PCF8563
172#define CONFIG_SYS_I2C_RTC_ADDR 0x51
173
174
175
176
177#ifdef CONFIG_TSEC1
178#define CONFIG_HAS_ETH0
179#define CONFIG_TSEC1_NAME "TSEC0"
180#define CONFIG_SYS_TSEC1_OFFSET 0x24000
181#define TSEC1_PHY_ADDR 0x1
182#define TSEC1_FLAGS TSEC_GIGABIT
183#define TSEC1_PHYIDX 0
184#endif
185
186#ifdef CONFIG_TSEC2
187#define CONFIG_HAS_ETH1
188#define CONFIG_TSEC2_NAME "TSEC1"
189#define CONFIG_SYS_TSEC2_OFFSET 0x25000
190#define TSEC2_PHY_ADDR 0x3
191#define TSEC2_FLAGS TSEC_GIGABIT
192#define TSEC2_PHYIDX 0
193#endif
194#define CONFIG_ETHPRIME "TSEC1"
195
196
197
198
199#define CONFIG_SYS_NS16550_SERIAL
200#define CONFIG_SYS_NS16550_REG_SIZE 1
201
202#define CONFIG_SYS_BAUDRATE_TABLE \
203 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
204#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
205#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
206#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
207
208#define CONFIG_HAS_FSL_DR_USB
209#define CONFIG_SYS_SCCR_USBDRCM 3
210
211
212
213
214#define CONFIG_BOOTP_BOOTFILESIZE
215
216
217
218
219#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
220#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
221#define CONFIG_SYS_MALLOC_LEN (8 * 1024 * 1024)
222
223
224
225
226
227#define CONFIG_NETDEV eth1
228#define CONFIG_HOSTNAME "ids8313"
229#define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx"
230#define CONFIG_BOOTFILE "ids8313/uImage"
231#define CONFIG_UBOOTPATH "ids8313/u-boot.bin"
232#define CONFIG_FDTFILE "ids8313/ids8313.dtb"
233#define CONFIG_LOADADDR 0x400000
234#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
235
236
237#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
238
239
240
241
242#define CONFIG_SYS_CBSIZE 1024
243#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
244
245#define CONFIG_SYS_MEMTEST_START 0x00001000
246#define CONFIG_SYS_MEMTEST_END 0x00C00000
247
248#define CONFIG_SYS_LOAD_ADDR 0x100000
249#define CONFIG_LOADS_ECHO
250#define CONFIG_TIMESTAMP
251#define CONFIG_BOOTCOMMAND "run boot_cramfs"
252#undef CONFIG_SYS_LOADS_BAUD_CHANGE
253
254#define CONFIG_JFFS2_NAND
255#define CONFIG_JFFS2_DEV "0"
256
257
258
259#define CONFIG_EXTRA_ENV_SETTINGS \
260 "netdev=" __stringify(CONFIG_NETDEV) "\0" \
261 "ethprime=TSEC1\0" \
262 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
263 "tftpflash=tftpboot ${loadaddr} ${uboot}; " \
264 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
265 " +${filesize}; " \
266 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
267 " +${filesize}; " \
268 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
269 " ${filesize}; " \
270 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
271 " +${filesize}; " \
272 "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
273 " ${filesize}\0" \
274 "console=ttyS0\0" \
275 "fdtaddr=0x780000\0" \
276 "kernel_addr=ff800000\0" \
277 "fdtfile=" __stringify(CONFIG_FDTFILE) "\0" \
278 "setbootargs=setenv bootargs " \
279 "root=${rootdev} rw console=${console}," \
280 "${baudrate} ${othbootargs}\0" \
281 "setipargs=setenv bootargs root=${rootdev} rw " \
282 "nfsroot=${serverip}:${rootpath} " \
283 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
284 "${netmask}:${hostname}:${netdev}:off " \
285 "console=${console},${baudrate} ${othbootargs}\0" \
286 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
287 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
288 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
289 "\0"
290
291#define CONFIG_NFSBOOTCOMMAND \
292 "setenv rootdev /dev/nfs;" \
293 "run setipargs;run addmtd;" \
294 "tftp ${loadaddr} ${bootfile};" \
295 "tftp ${fdtaddr} ${fdtfile};" \
296 "fdt addr ${fdtaddr};" \
297 "bootm ${loadaddr} - ${fdtaddr}"
298
299
300
301#endif
302
