LXR uboot/include/configs/km/km-mpc8309.h

   1/*
   2 * High Level Configuration Options
   3 */
   4#define CONFIG_E300             1       /* E300 family */
   5
   6#define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
   7
   8/*
   9 * System Clock Setup
  10 */
  11#define CONFIG_83XX_CLKIN               66000000
  12#define CONFIG_SYS_CLK_FREQ             66000000
  13#define CONFIG_83XX_PCICLK              66000000
  14
  15/* QE microcode/firmware address */
  16/* between the u-boot partition and env */
  17#ifndef CONFIG_SYS_QE_FW_ADDR
  18#define CONFIG_SYS_QE_FW_ADDR   0xF00C0000
  19#endif
  20
  21/*
  22 * System IO Config
  23 */
  24/* 0x14000180 SICR_1 */
  25#define CONFIG_SYS_SICRL (0                     \
  26                | SICR_1_UART1_UART1RTS         \
  27                | SICR_1_I2C_CKSTOP             \
  28                | SICR_1_IRQ_A_IRQ              \
  29                | SICR_1_IRQ_B_IRQ              \
  30                | SICR_1_GPIO_A_GPIO            \
  31                | SICR_1_GPIO_B_GPIO            \
  32                | SICR_1_GPIO_C_GPIO            \
  33                | SICR_1_GPIO_D_GPIO            \
  34                | SICR_1_GPIO_E_GPIO            \
  35                | SICR_1_GPIO_F_GPIO            \
  36                | SICR_1_USB_A_UART2S           \
  37                | SICR_1_USB_B_UART2RTS         \
  38                | SICR_1_FEC1_FEC1              \
  39                | SICR_1_FEC2_FEC2              \
  40                )
  41
  42/* 0x00080400 SICR_2 */
  43#define CONFIG_SYS_SICRH (0                     \
  44                | SICR_2_FEC3_FEC3              \
  45                | SICR_2_HDLC1_A_HDLC1          \
  46                | SICR_2_ELBC_A_LA              \
  47                | SICR_2_ELBC_B_LCLK            \
  48                | SICR_2_HDLC2_A_HDLC2          \
  49                | SICR_2_USB_D_GPIO             \
  50                | SICR_2_PCI_PCI                \
  51                | SICR_2_HDLC1_B_HDLC1          \
  52                | SICR_2_HDLC1_C_HDLC1          \
  53                | SICR_2_HDLC2_B_GPIO           \
  54                | SICR_2_HDLC2_C_HDLC2          \
  55                | SICR_2_QUIESCE_B              \
  56                )
  57
  58/* GPR_1 */
  59#define CONFIG_SYS_GPR1  0x50008060
  60
  61#define CONFIG_SYS_GP1DIR 0x00000000
  62#define CONFIG_SYS_GP1ODR 0x00000000
  63#define CONFIG_SYS_GP2DIR 0xFF000000
  64#define CONFIG_SYS_GP2ODR 0x00000000
  65
  66#define CONFIG_SYS_DDRCDR (\
  67        DDRCDR_EN | \
  68        DDRCDR_PZ_MAXZ | \
  69        DDRCDR_NZ_MAXZ | \
  70        DDRCDR_M_ODR)
  71
  72#define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
  73#define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
  74                                         SDRAM_CFG_32_BE | \
  75                                         SDRAM_CFG_SREN | \
  76                                         SDRAM_CFG_HSE)
  77
  78#define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
  79#define CONFIG_SYS_DDR_CLK_CNTL         (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  80#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
  81                                 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
  82
  83#define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
  84                                         CSCONFIG_ODT_RD_NEVER | \
  85                                         CSCONFIG_ODT_WR_ONLY_CURRENT | \
  86                                         CSCONFIG_ROW_BIT_13 | \
  87                                         CSCONFIG_COL_BIT_10)
  88
  89#define CONFIG_SYS_DDR_MODE     0x47860242
  90#define CONFIG_SYS_DDR_MODE2    0x8080c000
  91
  92#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
  93                                 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
  94                                 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
  95                                 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
  96                                 (0 << TIMING_CFG0_WWT_SHIFT) | \
  97                                 (0 << TIMING_CFG0_RRT_SHIFT) | \
  98                                 (0 << TIMING_CFG0_WRT_SHIFT) | \
  99                                 (0 << TIMING_CFG0_RWT_SHIFT))
 100
 101#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
 102                                 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 103                                 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 104                                 (3 << TIMING_CFG1_WRREC_SHIFT) | \
 105                                 (7 << TIMING_CFG1_REFREC_SHIFT) | \
 106                                 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 107                                 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 108                                 (3 << TIMING_CFG1_PRETOACT_SHIFT))
 109
 110#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 111                                 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 112                                 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 113                                 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 114                                 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 115                                 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 116                                 (5 << TIMING_CFG2_CPO_SHIFT))
 117
 118#define CONFIG_SYS_DDR_TIMING_3 0x00000000
 119
 120#define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
 121#define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 122
 123/* EEprom support */
 124#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 125
 126/* ethernet port connected to piggy (UEC2) */
 127#define CONFIG_HAS_ETH1
 128#define CONFIG_UEC_ETH2
 129#define CONFIG_SYS_UEC2_UCC_NUM         2       /* UCC3 */
 130#define CONFIG_SYS_UEC2_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 131#define CONFIG_SYS_UEC2_TX_CLK          QE_CLK12
 132#define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 133#define CONFIG_SYS_UEC2_PHY_ADDR        0
 134#define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 135#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 136